diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-12 12:17:14 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-12 17:47:11 +0200 |
| commit | df062afa03c9bccbe14919600ebadc2e3fe3db58 (patch) | |
| tree | 5c16e8cf84487f5b901ec20493adab3245a3cb0b | |
| parent | 3f76c0f47c9196556449c0e6e0bc5339028aff2a (diff) | |
radv/gfx10: enable vertex shaders without export parameters
GFX10 allows this.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index a58b0d6d006..63583a9c6d9 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3287,9 +3287,17 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index; + unsigned spi_vs_out_config, nparams; - radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, - S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1)); + /* VS is required to export at least one param. */ + nparams = MAX2(outinfo->param_exports, 1); + spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1); + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0); + } + + radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config); radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | @@ -3389,9 +3397,13 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, outinfo->writes_layer || outinfo->writes_viewport_index; bool break_wave_at_eoi = false; + unsigned nparams; + nparams = MAX2(outinfo->param_exports, 1); radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, - S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1)); + S_0286C4_VS_EXPORT_COUNT(nparams - 1) | + S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0)); + radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT, S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP)); radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, |