ac/radeonsi: move struct radeon_info to ac_gpu_info.h

Reviewed-by: Marek Olšák <[email protected]>

2 files changed, 94 insertions, 61 deletions

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
new file mode 100644
index 00000000000..608c4439f39
--- /dev/null
+++ b/src/amd/common/ac_gpu_info.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright © 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ */
+
+#ifndef AC_GPU_INFO_H
+#define AC_GPU_INFO_H
+
+#include "amd_family.h"
+
+#include <amdgpu.h>
+
+struct radeon_info {
+	/* PCI info: domain:bus:dev:func */
+	uint32_t                    pci_domain;
+	uint32_t                    pci_bus;
+	uint32_t                    pci_dev;
+	uint32_t                    pci_func;
+
+	/* Device info. */
+	uint32_t                    pci_id;
+	enum radeon_family          family;
+	enum chip_class             chip_class;
+	uint32_t                    gart_page_size;
+	uint64_t                    gart_size;
+	uint64_t                    vram_size;
+	uint64_t                    vram_vis_size;
+	uint64_t                    max_alloc_size;
+	uint32_t                    min_alloc_size;
+	bool                        has_dedicated_vram;
+	bool                        has_virtual_memory;
+	bool                        gfx_ib_pad_with_type2;
+	bool                        has_sdma;
+	bool                        has_uvd;
+	uint32_t                    uvd_fw_version;
+	uint32_t                    vce_fw_version;
+	uint32_t                    me_fw_version;
+	uint32_t                    pfp_fw_version;
+	uint32_t                    ce_fw_version;
+	uint32_t                    vce_harvest_config;
+	uint32_t                    clock_crystal_freq;
+	uint32_t                    tcc_cache_line_size;
+
+	/* Kernel info. */
+	uint32_t                    drm_major; /* version */
+	uint32_t                    drm_minor;
+	uint32_t                    drm_patchlevel;
+	bool                        has_userptr;
+
+	/* Shader cores. */
+	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
+	uint32_t                    max_shader_clock;
+	uint32_t                    num_good_compute_units;
+	uint32_t                    max_se; /* shader engines */
+	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
+
+	/* Render backends (color + depth blocks). */
+	uint32_t                    r300_num_gb_pipes;
+	uint32_t                    r300_num_z_pipes;
+	uint32_t                    r600_gb_backend_map; /* R600 harvest config */
+	bool                        r600_gb_backend_map_valid;
+	uint32_t                    r600_num_banks;
+	uint32_t                    num_render_backends;
+	uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
+	uint32_t                    pipe_interleave_bytes;
+	uint32_t                    enabled_rb_mask; /* GCN harvest config */
+
+	/* Tile modes. */
+	uint32_t                    si_tile_mode_array[32];
+	uint32_t                    cik_macrotile_mode_array[16];
+};
+
+#endif /* AC_GPU_INFO_H */
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 1d94b88ef4d..45ad561e236 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -28,7 +28,7 @@
 
 #include "pipebuffer/pb_buffer.h"
 
-#include "amd/common/amd_family.h"
+#include "amd/common/ac_gpu_info.h"
 #include "amd/common/ac_surface.h"
 
 #define RADEON_FLUSH_ASYNC		(1 << 0)
@@ -176,66 +176,6 @@ struct radeon_winsys_cs {
     uint64_t                      used_gart;
 };
 
-struct radeon_info {
-    /* PCI info: domain:bus:dev:func */
-    uint32_t                    pci_domain;
-    uint32_t                    pci_bus;
-    uint32_t                    pci_dev;
-    uint32_t                    pci_func;
-
-    /* Device info. */
-    uint32_t                    pci_id;
-    enum radeon_family          family;
-    enum chip_class             chip_class;
-    uint32_t                    gart_page_size;
-    uint64_t                    gart_size;
-    uint64_t                    vram_size;
-    uint64_t                    vram_vis_size;
-    uint64_t                    max_alloc_size;
-    uint32_t                    min_alloc_size;
-    bool                        has_dedicated_vram;
-    bool                        has_virtual_memory;
-    bool                        gfx_ib_pad_with_type2;
-    bool                        has_sdma;
-    bool                        has_uvd;
-    uint32_t                    uvd_fw_version;
-    uint32_t                    vce_fw_version;
-    uint32_t                    me_fw_version;
-    uint32_t                    pfp_fw_version;
-    uint32_t                    ce_fw_version;
-    uint32_t                    vce_harvest_config;
-    uint32_t                    clock_crystal_freq;
-    uint32_t                    tcc_cache_line_size;
-
-    /* Kernel info. */
-    uint32_t                    drm_major; /* version */
-    uint32_t                    drm_minor;
-    uint32_t                    drm_patchlevel;
-    bool                        has_userptr;
-
-    /* Shader cores. */
-    uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
-    uint32_t                    max_shader_clock;
-    uint32_t                    num_good_compute_units;
-    uint32_t                    max_se; /* shader engines */
-    uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
-
-    /* Render backends (color + depth blocks). */
-    uint32_t                    r300_num_gb_pipes;
-    uint32_t                    r300_num_z_pipes;
-    uint32_t                    r600_gb_backend_map; /* R600 harvest config */
-    bool                        r600_gb_backend_map_valid;
-    uint32_t                    r600_num_banks;
-    uint32_t                    num_render_backends;
-    uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
-    uint32_t                    pipe_interleave_bytes;
-    uint32_t                    enabled_rb_mask; /* GCN harvest config */
-
-    /* Tile modes. */
-    uint32_t                    si_tile_mode_array[32];
-    uint32_t                    cik_macrotile_mode_array[16];
-};
-
 /* Tiling info for display code, DRI sharing, and other data. */
 struct radeon_bo_metadata {
     /* Tiling flags describing the texture layout for display code