diff options
author | Rob Clark <[email protected]> | 2017-11-14 14:40:40 -0500 |
---|---|---|
committer | Rob Clark <[email protected]> | 2017-11-14 18:10:58 -0500 |
commit | d27318bdd087537a59ebce28a1cf9fd2daed7920 (patch) | |
tree | 242f1c23986e2cb004faa34f841d3a6c13189805 | |
parent | f383cf9d410e3764eda9321f75fd324f6a15138d (diff) |
freedreno/a5xx: indirect draw support
A couple failures in piglit tests w/ TF or gl_VertexID + indirect draws.
OTOH all the deqp tests (although they don't test those combinations).
I suspect this could be fixed by a firmware update, but I don't think
there is much we can do in mesa for that.
Signed-off-by: Rob Clark <[email protected]>
-rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_draw.h | 32 | ||||
-rw-r--r-- | src/gallium/drivers/freedreno/freedreno_screen.c | 6 |
2 files changed, 37 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h index de210e45654..e33085fcd5b 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h +++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h @@ -31,6 +31,8 @@ #include "freedreno_draw.h" +#include "fd5_context.h" + /* some bits in common w/ a4xx: */ #include "a4xx/fd4_draw.h" @@ -88,6 +90,36 @@ fd5_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring, enum pc_di_src_sel src_sel; uint32_t idx_size, idx_offset; + if (info->indirect) { + struct fd_resource *ind = fd_resource(info->indirect->buffer); + + emit_marker5(ring, 7); + + if (info->index_size) { + struct pipe_resource *idx = info->index.resource; + unsigned max_indicies = idx->width0 / info->index_size; + + OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6); + OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA, + fd4_size2indextype(info->index_size), 0), + &batch->draw_patches); + OUT_RELOC(ring, fd_resource(idx)->bo, + index_offset, 0, 0); + OUT_RING(ring, CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies)); + OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0); + } else { + OUT_PKT7(ring, CP_DRAW_INDIRECT, 3); + OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0), + &batch->draw_patches); + OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0); + } + + emit_marker5(ring, 7); + fd_reset_wfi(batch); + + return; + } + if (info->index_size) { assert(!info->has_user_indices); diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 159f272c9d7..0061b200596 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -276,7 +276,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: - case PIPE_CAP_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: @@ -330,6 +329,11 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: return 0; + case PIPE_CAP_DRAW_INDIRECT: + if (is_a5xx(screen)) + return 1; + return 0; + case PIPE_CAP_LOAD_CONSTBUF: /* name is confusing, but this turns on std430 packing */ if (is_ir3(screen)) |