diff options
| author | Samuel Pitoiset <[email protected]> | 2019-06-25 14:28:10 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-07-07 17:51:32 +0200 |
| commit | c90f46700dd2739ed9abb1246880d4829fdb3252 (patch) | |
| tree | bf4178e2b1d6d57490b92df75ef586da35b6f707 | |
| parent | b1b60a92b17e18f55c4d176e0b8445b6f486379a (diff) | |
radv/gfx10: mask DCC tile swizzle by alignment
DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 1f956e59954..f35d6ec4c32 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -4423,8 +4423,11 @@ radv_initialise_color_surface(struct radv_device *device, device->physical_device->rad_info.chip_class <= GFX8) va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset; + unsigned dcc_tile_swizzle = surf->tile_swizzle; + dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8; + cb->cb_dcc_base = va >> 8; - cb->cb_dcc_base |= surf->tile_swizzle; + cb->cb_dcc_base |= dcc_tile_swizzle; /* GFX10 field has the same base shift as the GFX6 field. */ uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; |