diff options
| author | Sagar Ghuge <[email protected]> | 2019-04-19 13:37:17 -0700 |
|---|---|---|
| committer | Sagar Ghuge <[email protected]> | 2019-10-21 20:32:43 -0700 |
| commit | bf943bdf24be0e663aa866e26f06f9fddcbef155 (patch) | |
| tree | ce073a77663b2a762d702ee66bc1240e2ca558c8 | |
| parent | c018c5a33920c765c33c66ed3e3d12ba38065e63 (diff) | |
intel/compiler: Set bits according to source file
On Gen >= 12, if src0 or src2 holds immediate value, we need set
src[0/2]_is_imm bits instead of register file.
Signed-off-by: Sagar Ghuge <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index c3debfe4d3d..ecd3c34470c 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -848,9 +848,19 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, src2.file == BRW_IMMEDIATE_VALUE); if (devinfo->gen >= 12) { - brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file); + if (src0.file == BRW_IMMEDIATE_VALUE) { + brw_inst_set_3src_a1_src0_is_imm(devinfo, inst, 1); + } else { + brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file); + } + brw_inst_set_3src_a1_src1_reg_file(devinfo, inst, src1.file); - brw_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file); + + if (src2.file == BRW_IMMEDIATE_VALUE) { + brw_inst_set_3src_a1_src2_is_imm(devinfo, inst, 1); + } else { + brw_inst_set_3src_a1_src2_reg_file(devinfo, inst, src2.file); + } } else { brw_inst_set_3src_a1_src0_reg_file(devinfo, inst, src0.file == BRW_GENERAL_REGISTER_FILE ? |