radv: emit correct centroid priority based on the number of samples

Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>

1 files changed, 16 insertions, 3 deletions

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 56d7a9a3682..9f6f92a42be 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -197,9 +197,6 @@ si_emit_graphics(struct radv_physical_device *physical_device,
 		radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
 				      S_008A14_CLIP_VTX_REORDER_ENA(1));
 
-	radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
-	radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
-
 	if (!physical_device->has_clear_state)
 		radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
 
@@ -1315,16 +1312,19 @@ void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
 static const uint32_t sample_locs_1x =
 	FILL_SREG(0, 0,   0, 0,   0, 0,   0, 0);
 static const unsigned max_dist_1x = 0;
+static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
 
 /* 2xMSAA */
 static const uint32_t sample_locs_2x =
 	FILL_SREG(4,4,   -4, -4,   0, 0,   0, 0);
 static const unsigned max_dist_2x = 4;
+static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
 
 /* 4xMSAA */
 static const uint32_t sample_locs_4x =
 	FILL_SREG(-2,-6,   6, -2,   -6, 2,  2, 6);
 static const unsigned max_dist_4x = 6;
+static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
 
 /* 8xMSAA */
 static const uint32_t sample_locs_8x[] = {
@@ -1336,6 +1336,7 @@ static const uint32_t sample_locs_8x[] = {
 	0,
 };
 static const unsigned max_dist_8x = 8;
+static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
 
 unsigned radv_get_default_max_sample_dist(int log_samples)
 {
@@ -1353,24 +1354,36 @@ void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples
 	switch (nr_samples) {
 	default:
 	case 1:
+		radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+		radeon_emit(cs, centroid_priority_1x);
+		radeon_emit(cs, centroid_priority_1x >> 32);
 		radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
 		radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
 		radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
 		radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
 		break;
 	case 2:
+		radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+		radeon_emit(cs, centroid_priority_2x);
+		radeon_emit(cs, centroid_priority_2x >> 32);
 		radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
 		radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
 		radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
 		radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
 		break;
 	case 4:
+		radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+		radeon_emit(cs, centroid_priority_4x);
+		radeon_emit(cs, centroid_priority_4x >> 32);
 		radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
 		radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
 		radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
 		radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
 		break;
 	case 8:
+		radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+		radeon_emit(cs, centroid_priority_8x);
+		radeon_emit(cs, centroid_priority_8x >> 32);
 		radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
 		radeon_emit_array(cs, sample_locs_8x, 4);
 		radeon_emit_array(cs, sample_locs_8x, 4);