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authorNicolai Hähnle <[email protected]>2017-10-24 11:43:30 +0000
committerMarek Olšák <[email protected]>2019-07-03 15:51:12 -0400
commitaf29ad7cc6b122bfdfd15ae4b67951c9c679a022 (patch)
treeb7885b360fc3b057d74993ded5bbba97eab84645
parent594010e366f911581ca0a4471a9d9fa68116514f (diff)
radeonsi/gfx10: set MAX_ALLOC_COUNT
The number for Vega was copied from PAL and has no effect because of MIN2. Acked-by: Bas Nieuwenhuizen <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 8726dd76498..07464d28056 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5190,23 +5190,35 @@ static void si_init_config(struct si_context *sctx)
if (sctx->chip_class >= GFX9) {
unsigned num_se = sscreen->info.max_se;
unsigned pc_lines = 0;
+ unsigned max_alloc_count = 0;
switch (sctx->family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
- pc_lines = 4096;
+ pc_lines = 2048;
break;
case CHIP_RAVEN:
case CHIP_RAVEN2:
+ case CHIP_NAVI10:
+ case CHIP_NAVI12:
pc_lines = 1024;
break;
+ case CHIP_NAVI14:
+ pc_lines = 512;
+ break;
default:
assert(0);
}
+ if (sctx->chip_class >= GFX10) {
+ max_alloc_count = pc_lines / 3;
+ } else {
+ max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
+ }
+
si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
- S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
+ S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
S_028C48_MAX_PRIM_PER_BATCH(1023));
si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));