amd/common: Introduce ac_get_fs_input_vgpr_cnt.

Add a function called ac_get_fs_input_vgpr_cnt which will return
the number of input VGPRs used by an AMD shader. Previously,
radv and radeonsi had the same code duplicated, but this commit also
allows them to share this code.

Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>

4 files changed, 63 insertions, 73 deletions

diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index e9fcae6469a..78b5006e0a1 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -205,3 +205,56 @@ ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim,
 	return dim;
 }
 
+unsigned
+ac_get_fs_input_vgpr_cnt(const struct ac_shader_config *config,
+			 signed char *face_vgpr_index_ptr,
+			 signed char *ancillary_vgpr_index_ptr)
+{
+	unsigned num_input_vgprs = 0;
+	signed char face_vgpr_index = -1;
+	signed char ancillary_vgpr_index = -1;
+
+	if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 2;
+	if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 2;
+	if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 2;
+	if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 3;
+	if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 2;
+	if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 2;
+	if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 2;
+	if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 1;
+	if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 1;
+	if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 1;
+	if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 1;
+	if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 1;
+	if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr)) {
+		face_vgpr_index = num_input_vgprs;
+		num_input_vgprs += 1;
+	}
+	if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr)) {
+		ancillary_vgpr_index = num_input_vgprs;
+		num_input_vgprs += 1;
+	}
+	if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 1;
+	if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
+		num_input_vgprs += 1;
+
+	if (face_vgpr_index_ptr)
+		*face_vgpr_index_ptr = face_vgpr_index;
+	if (ancillary_vgpr_index_ptr)
+		*ancillary_vgpr_index_ptr = ancillary_vgpr_index;
+
+	return num_input_vgprs;
+}
diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
index 9a9d3f1b232..b522aaa90fe 100644
--- a/src/amd/common/ac_shader_util.h
+++ b/src/amd/common/ac_shader_util.h
@@ -28,6 +28,7 @@
 #include <stdint.h>
 
 #include "amd_family.h"
+#include "ac_binary.h"
 #include "compiler/nir/nir.h"
 
 enum ac_image_dim {
@@ -63,4 +64,9 @@ enum ac_image_dim
 ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim,
 		 bool is_array);
 
+unsigned
+ac_get_fs_input_vgpr_cnt(const struct ac_shader_config *config,
+			 signed char *face_vgpr_index,
+			 signed char *ancillary_vgpr_index);
+
 #endif
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 0561b46ae85..eb0886bd1f8 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -663,39 +663,7 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
 	unsigned num_input_vgprs = info->num_input_vgprs;
 
 	if (stage == MESA_SHADER_FRAGMENT) {
-		num_input_vgprs = 0;
-		if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 2;
-		if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 2;
-		if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 2;
-		if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 3;
-		if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 2;
-		if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 2;
-		if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 2;
-		if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
-		if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr))
-			num_input_vgprs += 1;
+		num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
 	}
 
 	unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 49532b4c28a..fc45691d8d5 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7210,46 +7210,9 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 
 	/* Calculate the number of fragment input VGPRs. */
 	if (ctx.type == PIPE_SHADER_FRAGMENT) {
-		shader->info.num_input_vgprs = 0;
-		shader->info.face_vgpr_index = -1;
-		shader->info.ancillary_vgpr_index = -1;
-
-		if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 2;
-		if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 2;
-		if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 2;
-		if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 3;
-		if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 2;
-		if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 2;
-		if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 2;
-		if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 1;
-		if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 1;
-		if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 1;
-		if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 1;
-		if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 1;
-		if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
-			shader->info.face_vgpr_index = shader->info.num_input_vgprs;
-			shader->info.num_input_vgprs += 1;
-		}
-		if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
-			shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
-			shader->info.num_input_vgprs += 1;
-		}
-		if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 1;
-		if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
-			shader->info.num_input_vgprs += 1;
+		shader->info.num_input_vgprs = ac_get_fs_input_vgpr_cnt(&shader->config,
+						&shader->info.face_vgpr_index,
+						&shader->info.ancillary_vgpr_index);
 	}
 
 	si_calculate_max_simd_waves(shader);