diff options
| author | Lionel Landwerlin <[email protected]> | 2020-01-15 15:14:10 +0200 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2020-01-16 11:51:22 +0200 |
| commit | 9eca823cce84d7b055714ebda303f7e299a680d5 (patch) | |
| tree | b6c43f3442b2fe859ea49c9a595cbc8ddd324a55 | |
| parent | e6e5cbac04c950ecc37cb9de45c24d15a54cafc7 (diff) | |
iris: implement another workaround for non pipelined states
v2: add comment (Ken)
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index e872b14cf18..7ead920cadf 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -387,6 +387,8 @@ emit_state(struct iris_batch *batch, static void flush_before_state_base_change(struct iris_batch *batch) { + const struct gen_device_info *devinfo = &batch->screen->devinfo; + /* Flush before emitting STATE_BASE_ADDRESS. * * This isn't documented anywhere in the PRM. However, it seems to be @@ -412,7 +414,18 @@ flush_before_state_base_change(struct iris_batch *batch) "change STATE_BASE_ADDRESS (flushes)", PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | - PIPE_CONTROL_DATA_CACHE_FLUSH); + PIPE_CONTROL_DATA_CACHE_FLUSH | + /* GEN:BUG:1606662791: + * + * Software must program PIPE_CONTROL command + * with "HDC Pipeline Flush" prior to + * programming of the below two non-pipeline + * state : + * * STATE_BASE_ADDRESS + * * 3DSTATE_BINDING_TABLE_POOL_ALLOC + */ + ((GEN_GEN == 12 && devinfo->revision == 0 /* A0 */ ? + PIPE_CONTROL_FLUSH_HDC : 0))); } static void |