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authorKenneth Graunke <[email protected]>2015-11-30 15:26:50 -0800
committerKenneth Graunke <[email protected]>2015-12-07 14:48:55 -0800
commit87a1166310161d6ad703e802caa091850462ea55 (patch)
tree921016fae9f845d1c8cba0f4d3bad56cab562280
parent42ca675cc91af7ee06e2a47daa57d5d65bdd1c80 (diff)
i965: Add brw_device_info::min_ds_entries field.
From the 3DSTATE_URB_DS documentation: "Project: IVB, HSW If Domain Shader Thread Dispatch is Enabled then the minimum number of handles that must be allocated is 10 URB entries." "Project: BDW+ If Domain Shader Thread Dispatch is Enabled then the minimum number of handles that must be allocated is 34 URB entries." When the HS is run in SINGLE_PATCH mode (the only mode we support today), there is no minimum for HS - it's just zero. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_device_info.c11
-rw-r--r--src/mesa/drivers/dri/i965/brw_device_info.h1
2 files changed, 12 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
index 45505507be7..f4a935657c3 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -123,6 +123,7 @@ static const struct brw_device_info brw_device_info_ivb_gt1 = {
.min_vs_entries = 32,
.max_vs_entries = 512,
.max_hs_entries = 32,
+ .min_ds_entries = 10,
.max_ds_entries = 288,
.max_gs_entries = 192,
},
@@ -142,6 +143,7 @@ static const struct brw_device_info brw_device_info_ivb_gt2 = {
.min_vs_entries = 32,
.max_vs_entries = 704,
.max_hs_entries = 64,
+ .min_ds_entries = 10,
.max_ds_entries = 448,
.max_gs_entries = 320,
},
@@ -162,6 +164,7 @@ static const struct brw_device_info brw_device_info_byt = {
.min_vs_entries = 32,
.max_vs_entries = 512,
.max_hs_entries = 32,
+ .min_ds_entries = 10,
.max_ds_entries = 288,
.max_gs_entries = 192,
},
@@ -186,6 +189,7 @@ static const struct brw_device_info brw_device_info_hsw_gt1 = {
.min_vs_entries = 32,
.max_vs_entries = 640,
.max_hs_entries = 64,
+ .min_ds_entries = 10,
.max_ds_entries = 384,
.max_gs_entries = 256,
},
@@ -204,6 +208,7 @@ static const struct brw_device_info brw_device_info_hsw_gt2 = {
.min_vs_entries = 64,
.max_vs_entries = 1664,
.max_hs_entries = 128,
+ .min_ds_entries = 10,
.max_ds_entries = 960,
.max_gs_entries = 640,
},
@@ -222,6 +227,7 @@ static const struct brw_device_info brw_device_info_hsw_gt3 = {
.min_vs_entries = 64,
.max_vs_entries = 1664,
.max_hs_entries = 128,
+ .min_ds_entries = 10,
.max_ds_entries = 960,
.max_gs_entries = 640,
},
@@ -249,6 +255,7 @@ static const struct brw_device_info brw_device_info_bdw_gt1 = {
.min_vs_entries = 64,
.max_vs_entries = 2560,
.max_hs_entries = 504,
+ .min_ds_entries = 34,
.max_ds_entries = 1536,
.max_gs_entries = 960,
}
@@ -262,6 +269,7 @@ static const struct brw_device_info brw_device_info_bdw_gt2 = {
.min_vs_entries = 64,
.max_vs_entries = 2560,
.max_hs_entries = 504,
+ .min_ds_entries = 34,
.max_ds_entries = 1536,
.max_gs_entries = 960,
}
@@ -275,6 +283,7 @@ static const struct brw_device_info brw_device_info_bdw_gt3 = {
.min_vs_entries = 64,
.max_vs_entries = 2560,
.max_hs_entries = 504,
+ .min_ds_entries = 34,
.max_ds_entries = 1536,
.max_gs_entries = 960,
}
@@ -294,6 +303,7 @@ static const struct brw_device_info brw_device_info_chv = {
.min_vs_entries = 34,
.max_vs_entries = 640,
.max_hs_entries = 80,
+ .min_ds_entries = 34,
.max_ds_entries = 384,
.max_gs_entries = 256,
}
@@ -318,6 +328,7 @@ static const struct brw_device_info brw_device_info_chv = {
.min_vs_entries = 64, \
.max_vs_entries = 1856, \
.max_hs_entries = 672, \
+ .min_ds_entries = 34, \
.max_ds_entries = 1120, \
.max_gs_entries = 640, \
}
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.h b/src/mesa/drivers/dri/i965/brw_device_info.h
index 4911c233dea..af8520127a8 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.h
+++ b/src/mesa/drivers/dri/i965/brw_device_info.h
@@ -80,6 +80,7 @@ struct brw_device_info
unsigned min_vs_entries;
unsigned max_vs_entries;
unsigned max_hs_entries;
+ unsigned min_ds_entries;
unsigned max_ds_entries;
unsigned max_gs_entries;
} urb;