diff options
| author | Topi Pohjolainen <[email protected]> | 2015-12-09 14:44:21 +0200 |
|---|---|---|
| committer | Topi Pohjolainen <[email protected]> | 2016-05-12 19:49:22 +0300 |
| commit | 874c5f05dbc8eca2d14a14f32fdd964808c53b7e (patch) | |
| tree | ccde052139ec4f4cfc82eb1a337e2e033a74e4ec | |
| parent | a8544267fd7936885db3b192c85c1b1f488039a4 (diff) | |
i965/gen9: Prepare surface state setup for lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
v3 (Ben): Do not set fast claer state in surface state setup.
Moved into brw_postdraw_set_buffers_need_resolve()
using a separate patch.
v4: Support for blorp
v5 (Ben): Re-use gen8_get_aux_mode()
Signed-off-by: Topi Pohjolainen <[email protected]>
Reviewed-by: Ben Widawsky <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_blorp.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 |
3 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 4696faf082e..fce510c8fe0 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -656,6 +656,7 @@ #define GEN8_SURFACE_AUX_MODE_MCS 1 #define GEN8_SURFACE_AUX_MODE_APPEND 2 #define GEN8_SURFACE_AUX_MODE_HIZ 3 +#define GEN9_SURFACE_AUX_MODE_CCS_E 5 /* Surface state DW7 */ #define GEN9_SURFACE_RT_COMPRESSION_SHIFT 30 diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c index 5cd070fa473..05ef54c4d0a 100644 --- a/src/mesa/drivers/dri/i965/gen8_blorp.c +++ b/src/mesa/drivers/dri/i965/gen8_blorp.c @@ -77,7 +77,7 @@ gen8_blorp_emit_surface_state(struct brw_context *brw, surf[6] = SET_FIELD(surface->mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) | SET_FIELD((surface->mt->mcs_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) | - GEN8_SURFACE_AUX_MODE_MCS; + gen8_get_aux_mode(brw, mt); } else { surf[6] = 0; } diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 4f9a6e96fe9..4b9896fe7d6 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -216,6 +216,9 @@ gen8_get_aux_mode(const struct brw_context *brw, if (brw->gen >= 9 || mt->num_samples == 1) assert(mt->halign == 16); + if (intel_miptree_is_lossless_compressed(brw, mt)) + return GEN9_SURFACE_AUX_MODE_CCS_E; + return GEN8_SURFACE_AUX_MODE_MCS; } |