freedreno/ir3: Pre-color TCS header and primitive ID inputs

Similar to GS, the registers are shared and not reinitialized betewen
VS and TCS, so we need to make sure to allocate the same registers for
the system values between stages.

Signed-off-by: Kristian H. Kristensen <[email protected]>
Acked-by: Eric Anholt <[email protected]>
Reviewed-by: Rob Clark <[email protected]>

1 files changed, 12 insertions, 2 deletions

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 66b274d1787..3b0dc5a0c8c 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -3435,9 +3435,19 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 		}
 
 		ret = ir3_ra(so, ir->inputs, ir->ninputs);
+	} else if (ctx->tcs_header) {
+		/* We need to have these values in the same registers between VS and TCS
+		 * since the VS chains to TCS and doesn't get the sysvals redelivered.
+		 */
+
+		ctx->tcs_header->regs[0]->num = 0;
+		ctx->primitive_id->regs[0]->num = 1;
+		struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
+		ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
 	} else if (ctx->gs_header) {
-		/* We need to have these values in the same registers between VS and GS
-		 * since the VS chains to GS and doesn't get the sysvals redelivered.
+		/* We need to have these values in the same registers between producer
+		 * (VS or DS) and GS since the producer chains to GS and doesn't get
+		 * the sysvals redelivered.
 		 */
 
 		ctx->gs_header->regs[0]->num = 0;