summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorIlia Mirkin <[email protected]>2017-02-11 18:20:50 -0500
committerIlia Mirkin <[email protected]>2017-02-11 21:06:41 -0500
commit7e75f0913ab545be14feb233d1ed74dc48116fb8 (patch)
treeb990da999995e9b60d9ad4f4899d1e9f9b4a4d07
parentb38aab50a04b63038a42b7e4da3f8b5e9dbb8f24 (diff)
gm107/ir: fix address offset bitfield for ATOMS
Fixes GL45-CTS.compute_shader.atomic-case1 on Maxwell Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index f36838cbf8d..6de3f396e3e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -2538,7 +2538,7 @@ CodeEmitterGM107::emitATOMS()
emitField(0x34, 4, subOp);
emitGPR (0x14, insn->src(1));
- emitADDR (0x08, 0x12, 22, 0, insn->src(0));
+ emitADDR (0x08, 0x1e, 22, 2, insn->src(0));
emitGPR (0x00, insn->def(0));
}