diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-01 16:31:01 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-02 09:38:02 +0200 |
| commit | 6cc213b3c123a636baf07511c8e17ca32fb5da5a (patch) | |
| tree | db040f5a884bdf71c26ddb484ee0d998aae418c0 | |
| parent | 233224c7f7c2dcd609f6832265fbe9fede58dae4 (diff) | |
radv: enable DCC for layers on GFX8
It's currently only enabled if dcc_slice_size is equal to
dcc_slice_fast_clear_size because the driver assumes that
portions of multiple layers are contiguous but it's not
always true.
Still not supported on GFX9.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 32 |
1 files changed, 23 insertions, 9 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 07d89d32edf..eeccce0d82f 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -171,14 +171,10 @@ radv_use_dcc_for_image(struct radv_device *device, return false; /* TODO: Enable DCC for mipmaps on GFX9+. */ - if (pCreateInfo->mipLevels > 1 && + if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) && device->physical_device->rad_info.chip_class >= GFX9) return false; - /* TODO: Enable DCC for array layers. */ - if (pCreateInfo->arrayLayers > 1) - return false; - /* Do not enable DCC for mipmapped arrays because performance is worse. */ if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1) return false; @@ -1018,10 +1014,28 @@ radv_image_can_enable_dcc_or_cmask(struct radv_image *image) } static inline bool -radv_image_can_enable_dcc(struct radv_image *image) +radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image) { - return radv_image_can_enable_dcc_or_cmask(image) && - radv_image_has_dcc(image); + if (!radv_image_can_enable_dcc_or_cmask(image) || + !radv_image_has_dcc(image)) + return false; + + /* On GFX8, DCC layers can be interleaved and it's currently only + * enabled if slice size is equal to the per slice fast clear size + * because the driver assumes that portions of multiple layers are + * contiguous during fast clears. + */ + if (image->info.array_size > 1) { + const struct legacy_surf_level *surf_level = + &image->planes[0].surface.u.legacy.level[0]; + + assert(device->physical_device->rad_info.chip_class == GFX8); + + if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size) + return false; + } + + return true; } static inline bool @@ -1151,7 +1165,7 @@ radv_image_create(VkDevice _device, if (!create_info->no_metadata_planes) { /* Try to enable DCC first. */ - if (radv_image_can_enable_dcc(image)) { + if (radv_image_can_enable_dcc(device, image)) { radv_image_alloc_dcc(image); if (image->info.samples > 1) { /* CMASK should be enabled because DCC fast |