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authorRob Clark <robdclark@gmail.com>2018-11-23 11:30:34 -0500
committerRob Clark <robdclark@gmail.com>2018-11-27 15:44:03 -0500
commit5973a4d0b7df54264b7f314153363877bfe6b8ad (patch)
treee20d5e8285af9fba517a79c0e5677acdedc2c032
parente68cd912518b924e025947adf7c3accc69993bba (diff)
freedreno/a3xx: also set FSSUPERTHREADENABLE
We set equiv bit in SP_FS_CTRL_REG0. Somehow the hw doesn't hang with this mismatched config, but does run slower. It is faster with either neither bit set, or both bits set, but both is the fastest of the three configurations. Worth a bit over 10% gain in glmark2. Spotted-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_program.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index edc3a4dd6c4..95825847857 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -226,6 +226,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
+ A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
/* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
* flush some caches? I think we only need to set those