diff options
author | Christoph Bumiller <e0425955@student.tuwien.ac.at> | 2011-03-05 00:05:14 +0100 |
---|---|---|
committer | Christoph Bumiller <e0425955@student.tuwien.ac.at> | 2011-03-05 00:51:07 +0100 |
commit | 4fae7da9a3a3849ca08ffc6fcbdccc6a9c065ad2 (patch) | |
tree | 7984f66e7203617e7cb43924db4727ff4370036f | |
parent | 9f0acfe1384d3236ac30ffca4be96e9531d2e876 (diff) |
nv50,nvc0: fix texture layer issues
-rw-r--r-- | src/gallium/drivers/nv50/nv50_tex.c | 14 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_3d.xml.h | 20 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_miptree.c | 39 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_resource.h | 3 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_screen.c | 2 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_state_validate.c | 10 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_stateobj.h | 2 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_surface.c | 27 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_tex.c | 15 | ||||
-rw-r--r-- | src/gallium/drivers/nvc0/nvc0_transfer.c | 22 |
10 files changed, 89 insertions, 65 deletions
diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c index 4456553a868..d9bb3aabafe 100644 --- a/src/gallium/drivers/nv50/nv50_tex.c +++ b/src/gallium/drivers/nv50/nv50_tex.c @@ -90,7 +90,7 @@ nv50_create_sampler_view(struct pipe_context *pipe, (swz[2] << NV50_TIC_0_MAPB__SHIFT) | (swz[3] << NV50_TIC_0_MAPA__SHIFT); - /* tic[1] = mt->base.bo->offset; */ + tic[1] = /* mt->base.bo->offset; */ 0; tic[2] = /* mt->base.bo->offset >> 32 */ 0; tic[2] |= 0x10001000 | /* NV50_TIC_2_NO_BORDER */ 0x40000000; @@ -107,6 +107,12 @@ nv50_create_sampler_view(struct pipe_context *pipe, depth = MAX2(mt->base.base.array_size, mt->base.base.depth0); + if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY || + mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) { + tic[1] = view->pipe.u.tex.first_layer * mt->layer_stride; + depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1; + } + switch (mt->base.base.target) { case PIPE_TEXTURE_1D: tic[2] |= NV50_TIC_2_TARGET_1D; @@ -178,6 +184,8 @@ nv50_validate_tic(struct nv50_context *nv50, int s) res = &nv50_miptree(tic->pipe.texture)->base; if (tic->id < 0) { + uint32_t offset = tic->tic[1]; + tic->id = nv50_screen_tic_alloc(nv50->screen, tic); MARK_RING (chan, 24 + 8, 4); @@ -206,8 +214,8 @@ nv50_validate_tic(struct nv50_context *nv50, int s) OUT_RING (chan, 0); BEGIN_RING_NI(chan, RING_2D(SIFC_DATA), 8); OUT_RING (chan, tic->tic[0]); - OUT_RELOCl(chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); - OUT_RELOC (chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | + OUT_RELOCl(chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); + OUT_RELOC (chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH | NOUVEAU_BO_OR, tic->tic[2], tic->tic[2]); OUT_RINGp (chan, &tic->tic[3], 5); diff --git a/src/gallium/drivers/nvc0/nvc0_3d.xml.h b/src/gallium/drivers/nvc0/nvc0_3d.xml.h index 73a605f94e1..5857f7cee9e 100644 --- a/src/gallium/drivers/nvc0/nvc0_3d.xml.h +++ b/src/gallium/drivers/nvc0/nvc0_3d.xml.h @@ -154,8 +154,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_LOCAL_SIZE_LOW 0x0000079c -#define NVC0_3D_RT(i0) (0x00000800 + 0x20*(i0)) -#define NVC0_3D_RT__ESIZE 0x00000020 +#define NVC0_3D_RT(i0) (0x00000800 + 0x40*(i0)) +#define NVC0_3D_RT__ESIZE 0x00000040 #define NVC0_3D_RT__LEN 0x00000008 #define NVC0_3D_RT_ADDRESS_HIGH(i0) (0x00000800 + 0x40*(i0)) @@ -169,11 +169,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_RT_FORMAT(i0) (0x00000810 + 0x40*(i0)) #define NVC0_3D_RT_TILE_MODE(i0) (0x00000814 + 0x40*(i0)) -#define NVC0_3D_RT_TILE_MODE_UNK0 0x00000001 +#define NVC0_3D_RT_TILE_MODE_X 0x00000001 #define NVC0_3D_RT_TILE_MODE_Y__MASK 0x00000070 #define NVC0_3D_RT_TILE_MODE_Y__SHIFT 4 #define NVC0_3D_RT_TILE_MODE_Z__MASK 0x00000700 #define NVC0_3D_RT_TILE_MODE_Z__SHIFT 8 +#define NVC0_3D_RT_TILE_MODE_LINEAR 0x00001000 +#define NVC0_3D_RT_TILE_MODE_UNK16 0x00010000 #define NVC0_3D_RT_ARRAY_MODE(i0) (0x00000818 + 0x40*(i0)) #define NVC0_3D_RT_ARRAY_MODE_LAYERS__MASK 0x0000ffff @@ -182,6 +184,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_RT_LAYER_STRIDE(i0) (0x0000081c + 0x40*(i0)) +#define NVC0_3D_RT_BASE_LAYER(i0) (0x00000820 + 0x40*(i0)) + +#define NVC0_3D_RT_UNK14(i0) (0x00000824 + 0x40*(i0)) + #define NVC0_3D_VIEWPORT_SCALE_X(i0) (0x00000a00 + 0x20*(i0)) #define NVC0_3D_VIEWPORT_SCALE_X__ESIZE 0x00000020 #define NVC0_3D_VIEWPORT_SCALE_X__LEN 0x00000010 @@ -795,8 +801,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_POLYGON_OFFSET_UNITS 0x000015bc -#define NVC0_3D_GP_BUILTIN_RESULT_EN 0x000015cc -#define NVC0_3D_GP_BUILTIN_RESULT_EN_LAYER 0x00010000 +#define NVC0_3D_LAYER 0x000015cc +#define NVC0_3D_LAYER_IDX__MASK 0x0000ffff +#define NVC0_3D_LAYER_IDX__SHIFT 0 +#define NVC0_3D_LAYER_USE_GP 0x00010000 #define NVC0_3D_MULTISAMPLE_MODE 0x000015d0 #define NVC0_3D_MULTISAMPLE_MODE_1X 0x00000000 @@ -917,6 +925,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_POLYGON_STIPPLE_PATTERN__ESIZE 0x00000004 #define NVC0_3D_POLYGON_STIPPLE_PATTERN__LEN 0x00000020 +#define NVC0_3D_ZETA_BASE_LAYER 0x0000179c + #define NVC0_3D_STRMOUT_UNK1780(i0) (0x00001780 + 0x4*(i0)) #define NVC0_3D_STRMOUT_UNK1780__ESIZE 0x00000004 #define NVC0_3D_STRMOUT_UNK1780__LEN 0x00000004 diff --git a/src/gallium/drivers/nvc0/nvc0_miptree.c b/src/gallium/drivers/nvc0/nvc0_miptree.c index ea3ed9e0225..db9117c3ff1 100644 --- a/src/gallium/drivers/nvc0/nvc0_miptree.c +++ b/src/gallium/drivers/nvc0/nvc0_miptree.c @@ -57,17 +57,25 @@ get_tile_dims(unsigned nx, unsigned ny, unsigned nz) return tile_mode | 0x100; } -static INLINE unsigned -calc_zslice_offset(uint32_t tile_mode, unsigned z, unsigned pitch, unsigned nbh) +uint32_t +nvc0_miptree_zslice_offset(struct nvc0_miptree *mt, unsigned l, unsigned z) { - unsigned tile_h = NVC0_TILE_HEIGHT(tile_mode); - unsigned tile_d_shift = NVC0_TILE_DIM_SHIFT(tile_mode, 2); + unsigned nblocksy; /* height of texture level aligned to tile height */ + + unsigned stride_2d; /* to next slice within a 3D tile */ + unsigned stride_3d; /* to slice in the next (in z direction !) 3D tile */ + + unsigned tile_d_shift = NVC0_TILE_DIM_SHIFT(mt->level[l].tile_mode, 2); unsigned tile_d = 1 << tile_d_shift; - /* stride_2d == to next slice within this volume tile */ - /* stride_3d == size (in bytes) of a volume tile */ - unsigned stride_2d = tile_h * NVC0_TILE_PITCH(tile_mode); - unsigned stride_3d = tile_d * align(nbh, tile_h) * pitch; + nblocksy = util_format_get_nblocksy(mt->base.base.format, + u_minify(mt->base.base.height0, l)); + + nblocksy = align(nblocksy, NVC0_TILE_HEIGHT(mt->level[l].tile_mode)); + + stride_2d = NVC0_TILE_SIZE_2D(mt->level[l].tile_mode); + + stride_3d = (nblocksy * mt->level[l].pitch) << tile_d_shift; return (z & (tile_d - 1)) * stride_2d + (z >> tile_d_shift) * stride_3d; } @@ -298,21 +306,6 @@ nvc0_miptree_surface_new(struct pipe_context *pipe, ps->width = ns->width; ps->height = ns->height; - if (mt->layout_3d) { - unsigned zslice = ps->u.tex.first_layer; - - /* TODO: re-layout the texture to use only depth 1 tiles in this case: */ - if (ns->depth > 1 && (zslice & (NVC0_TILE_DEPTH(lvl->tile_mode) - 1))) - NOUVEAU_ERR("Creating unsupported 3D surface of slices [%u:%u].\n", - zslice, ps->u.tex.last_layer); - - ns->offset += calc_zslice_offset(lvl->tile_mode, zslice, lvl->pitch, - util_format_get_nblocksy(pt->format, - ns->height)); - } else { - ns->offset += mt->layer_stride * ps->u.tex.first_layer; - } - return ps; } diff --git a/src/gallium/drivers/nvc0/nvc0_resource.h b/src/gallium/drivers/nvc0/nvc0_resource.h index 7821db51b72..f1c445b5152 100644 --- a/src/gallium/drivers/nvc0/nvc0_resource.h +++ b/src/gallium/drivers/nvc0/nvc0_resource.h @@ -69,4 +69,7 @@ nvc0_miptree_surface_new(struct pipe_context *, void nvc0_miptree_surface_del(struct pipe_context *, struct pipe_surface *); +uint32_t +nvc0_miptree_zslice_offset(struct nvc0_miptree *, unsigned l, unsigned z); + #endif diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index 923bb83e8a3..bf4e796adf5 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -582,7 +582,7 @@ nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) OUT_RING (chan, 1); BEGIN_RING(chan, RING_3D(GP_SELECT), 1); OUT_RING (chan, 0x40); - BEGIN_RING(chan, RING_3D(GP_BUILTIN_RESULT_EN), 1); + BEGIN_RING(chan, RING_3D(LAYER), 1); OUT_RING (chan, 0); BEGIN_RING(chan, RING_3D(TEP_SELECT), 1); OUT_RING (chan, 0x30); diff --git a/src/gallium/drivers/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nvc0/nvc0_state_validate.c index ab8119a3bbb..6fd880829e4 100644 --- a/src/gallium/drivers/nvc0/nvc0_state_validate.c +++ b/src/gallium/drivers/nvc0/nvc0_state_validate.c @@ -76,7 +76,7 @@ nvc0_validate_fb(struct nvc0_context *nvc0) struct nouveau_bo *bo = mt->base.bo; uint32_t offset = sf->offset; - BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 8); + BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(i)), 9); OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); OUT_RING (chan, sf->width); @@ -84,8 +84,9 @@ nvc0_validate_fb(struct nvc0_context *nvc0) OUT_RING (chan, nvc0_format_table[sf->base.format].rt); OUT_RING (chan, (mt->layout_3d << 16) | mt->level[sf->base.u.tex.level].tile_mode); - OUT_RING (chan, sf->depth); + OUT_RING (chan, sf->base.u.tex.first_layer + sf->depth); OUT_RING (chan, mt->layer_stride >> 2); + OUT_RING (chan, sf->base.u.tex.first_layer); if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) serialize = TRUE; @@ -115,7 +116,10 @@ nvc0_validate_fb(struct nvc0_context *nvc0) BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3); OUT_RING (chan, sf->width); OUT_RING (chan, sf->height); - OUT_RING (chan, (unk << 16) | sf->depth); + OUT_RING (chan, (unk << 16) | + (sf->base.u.tex.first_layer + sf->depth)); + BEGIN_RING(chan, RING_3D(ZETA_BASE_LAYER), 1); + OUT_RING (chan, sf->base.u.tex.first_layer); if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) serialize = TRUE; diff --git a/src/gallium/drivers/nvc0/nvc0_stateobj.h b/src/gallium/drivers/nvc0/nvc0_stateobj.h index 57566128ab5..c0c77a2ee18 100644 --- a/src/gallium/drivers/nvc0/nvc0_stateobj.h +++ b/src/gallium/drivers/nvc0/nvc0_stateobj.h @@ -34,7 +34,7 @@ nvc0_tsc_entry(void *hwcso) struct nvc0_tic_entry { struct pipe_sampler_view pipe; int id; - uint32_t tic[8]; + uint32_t tic[8]; /* tic[1] (low 32 bit of address) is used for offset */ }; static INLINE struct nvc0_tic_entry * diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c b/src/gallium/drivers/nvc0/nvc0_surface.c index a4b2b948123..67991a0b5a6 100644 --- a/src/gallium/drivers/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nvc0/nvc0_surface.c @@ -91,14 +91,18 @@ nvc0_2d_texture_set(struct nouveau_channel *chan, int dst, width = u_minify(mt->base.base.width0, level); height = u_minify(mt->base.base.height0, level); + depth = u_minify(mt->base.base.depth0, level); + + /* layer has to be < depth, and depth > tile depth / 2 */ - offset = mt->level[level].offset; if (!mt->layout_3d) { offset += mt->layer_stride * layer; + layer = 0; depth = 1; + } else + if (!dst) { + offset += nvc0_miptree_zslice_offset(mt, level, layer); layer = 0; - } else { - depth = u_minify(mt->base.base.depth0, level); } if (!(bo->tile_flags & NOUVEAU_BO_TILE_LAYOUT_MASK)) { @@ -233,15 +237,17 @@ nvc0_clear_render_target(struct pipe_context *pipe, BEGIN_RING(chan, RING_3D(RT_CONTROL), 1); OUT_RING (chan, 1); - BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(0)), 8); + BEGIN_RING(chan, RING_3D(RT_ADDRESS_HIGH(0)), 9); OUT_RELOCh(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); OUT_RING (chan, sf->width); OUT_RING (chan, sf->height); OUT_RING (chan, nvc0_format_table[dst->format].rt); - OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode); - OUT_RING (chan, 1); - OUT_RING (chan, 0); + OUT_RING (chan, (mt->layout_3d << 16) | + mt->level[sf->base.u.tex.level].tile_mode); + OUT_RING (chan, dst->u.tex.first_layer + sf->depth); + OUT_RING (chan, mt->layer_stride >> 2); + OUT_RING (chan, dst->u.tex.first_layer); BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 2); OUT_RING (chan, ((dstx + width) << 16) | dstx); @@ -272,6 +278,7 @@ nvc0_clear_depth_stencil(struct pipe_context *pipe, struct nvc0_surface *sf = nvc0_surface(dst); struct nouveau_bo *bo = mt->base.bo; uint32_t mode = 0; + int unk = mt->base.base.target == PIPE_TEXTURE_2D; if (clear_flags & PIPE_CLEAR_DEPTH) { BEGIN_RING(chan, RING_3D(CLEAR_DEPTH), 1); @@ -293,13 +300,15 @@ nvc0_clear_depth_stencil(struct pipe_context *pipe, OUT_RELOCl(chan, bo, sf->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); OUT_RING (chan, nvc0_format_table[dst->format].rt); OUT_RING (chan, mt->level[sf->base.u.tex.level].tile_mode); - OUT_RING (chan, 0); + OUT_RING (chan, mt->layer_stride >> 2); BEGIN_RING(chan, RING_3D(ZETA_ENABLE), 1); OUT_RING (chan, 1); BEGIN_RING(chan, RING_3D(ZETA_HORIZ), 3); OUT_RING (chan, sf->width); OUT_RING (chan, sf->height); - OUT_RING (chan, (1 << 16) | 1); + OUT_RING (chan, (unk << 16) | (dst->u.tex.first_layer + sf->depth)); + BEGIN_RING(chan, RING_3D(ZETA_BASE_LAYER), 1); + OUT_RING (chan, dst->u.tex.first_layer); BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 2); OUT_RING (chan, ((dstx + width) << 16) | dstx); diff --git a/src/gallium/drivers/nvc0/nvc0_tex.c b/src/gallium/drivers/nvc0/nvc0_tex.c index 6822e597b36..c52c76597a3 100644 --- a/src/gallium/drivers/nvc0/nvc0_tex.c +++ b/src/gallium/drivers/nvc0/nvc0_tex.c @@ -89,7 +89,7 @@ nvc0_create_sampler_view(struct pipe_context *pipe, (swz[2] << NV50_TIC_0_MAPB__SHIFT) | (swz[3] << NV50_TIC_0_MAPA__SHIFT); - /* tic[1] = mt->base.bo->offset; */ + tic[1] = /* mt->base.bo->offset; */ 0; tic[2] = /* mt->base.bo->offset >> 32 */ 0; tic[2] |= 0x10001000 | /* NV50_TIC_2_NO_BORDER */ 0x40000000; @@ -106,6 +106,13 @@ nvc0_create_sampler_view(struct pipe_context *pipe, depth = MAX2(mt->base.base.array_size, mt->base.base.depth0); + if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY || + mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) { + /* there doesn't seem to be a base layer field in TIC */ + tic[1] = view->pipe.u.tex.first_layer * mt->layer_stride; + depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1; + } + switch (mt->base.base.target) { case PIPE_TEXTURE_1D: tic[2] |= NV50_TIC_2_TARGET_1D; @@ -177,6 +184,8 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s) res = &nvc0_miptree(tic->pipe.texture)->base; if (tic->id < 0) { + uint32_t offset = tic->tic[1]; + tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic); MARK_RING (chan, 9 + 8, 4); @@ -190,8 +199,8 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s) OUT_RING (chan, 0x100111); BEGIN_RING_NI(chan, RING_MF(DATA), 8); OUT_RING (chan, tic->tic[0]); - OUT_RELOCl(chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); - OUT_RELOC (chan, res->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | + OUT_RELOCl(chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); + OUT_RELOC (chan, res->bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH | NOUVEAU_BO_OR, tic->tic[2], tic->tic[2]); OUT_RINGp (chan, &tic->tic[3], 5); diff --git a/src/gallium/drivers/nvc0/nvc0_transfer.c b/src/gallium/drivers/nvc0/nvc0_transfer.c index a38bdb8f0a6..bc642669e5b 100644 --- a/src/gallium/drivers/nvc0/nvc0_transfer.c +++ b/src/gallium/drivers/nvc0/nvc0_transfer.c @@ -243,35 +243,23 @@ nvc0_miptree_transfer_new(struct pipe_context *pctx, struct nvc0_miptree_level *lvl = &mt->level[level]; struct nvc0_transfer *tx; uint32_t size; - uint32_t w, h, d, z, layer, box_h, box_y; + uint32_t w, h, d, z, layer; int ret; tx = CALLOC_STRUCT(nvc0_transfer); if (!tx) return NULL; - box_y = box->y; - box_h = box->height; - if (mt->layout_3d) { z = box->z; d = u_minify(res->depth0, level); layer = 0; - tx->nlayers = box->depth; } else { z = 0; d = 1; - if (res->target == PIPE_TEXTURE_1D || - res->target == PIPE_TEXTURE_1D_ARRAY) { - box_y = 0; - box_h = 1; - layer = box->y; - tx->nlayers = box->height; - } else { - layer = box->z; - tx->nlayers = box->depth; - } + layer = box->z; } + tx->nlayers = box->depth; pipe_resource_reference(&tx->base.resource, res); @@ -280,7 +268,7 @@ nvc0_miptree_transfer_new(struct pipe_context *pctx, tx->base.box = *box; tx->nblocksx = util_format_get_nblocksx(res->format, box->width); - tx->nblocksy = util_format_get_nblocksy(res->format, box_h); + tx->nblocksy = util_format_get_nblocksy(res->format, box->height); tx->base.stride = tx->nblocksx * util_format_get_blocksize(res->format); tx->base.layer_stride = tx->nblocksy * tx->base.stride; @@ -294,7 +282,7 @@ nvc0_miptree_transfer_new(struct pipe_context *pctx, tx->rect[0].base = lvl->offset + layer * mt->layer_stride; tx->rect[0].tile_mode = lvl->tile_mode; tx->rect[0].x = util_format_get_nblocksx(res->format, box->x); - tx->rect[0].y = util_format_get_nblocksy(res->format, box_y); + tx->rect[0].y = util_format_get_nblocksy(res->format, box->y); tx->rect[0].z = z; tx->rect[0].width = util_format_get_nblocksx(res->format, w); tx->rect[0].height = util_format_get_nblocksy(res->format, h); |