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authorTom Stellard <thomas.stellard@amd.com>2012-09-04 11:20:01 -0400
committerTom Stellard <thomas.stellard@amd.com>2012-09-04 14:21:10 -0400
commit446d19c12a576e36c3da34ada01b708fcbc196c5 (patch)
tree452e664149d5db135852d748c51b60f29a0a3d3f
parentf9fede884b7ace711ccf63152afdbdaf209edced (diff)
radeon/llvm: Fix lowering of SI_V_CNDLT
SREG_LIT_0 is a scalar register, so it can only be used in the first argument of vector instructoins.
-rw-r--r--src/gallium/drivers/radeon/SIISelLowering.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp
index a64e2a378ff..2c8167382c7 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -235,10 +235,10 @@ void SITargetLowering::LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB,
void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
{
- BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32),
+ BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_GT_F32_e32),
AMDGPU::VCC)
- .addOperand(MI->getOperand(1))
- .addReg(AMDGPU::SREG_LIT_0);
+ .addReg(AMDGPU::SREG_LIT_0)
+ .addOperand(MI->getOperand(1));
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
.addOperand(MI->getOperand(0))