diff options
| author | Alyssa Rosenzweig <[email protected]> | 2018-11-11 11:09:40 -0800 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2018-11-12 10:28:04 -0800 |
| commit | 41c8f991379d1a714cb6c161edfacca1dd296d87 (patch) | |
| tree | 9e38370ef0a4f1f2a3659fa1dbeb4b662942e245 | |
| parent | 9c2a95b29868f1388408b5eb9193fff39f942217 (diff) | |
util: Fix warning in u_cpu_detect on non-x86
regs is only set and used on x86; on other platforms (like ARM), this
code causes a trivial warning, solved by moving the regs declaration to
the architecture-dependent usage.
Reviewed-by: Matt Turner <[email protected]>
Signed-off-by: Alyssa Rosenzweig <[email protected]>
| -rw-r--r-- | src/util/u_cpu_detect.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c index 4dbb4d8fb58..52b9ae547d4 100644 --- a/src/util/u_cpu_detect.c +++ b/src/util/u_cpu_detect.c @@ -370,14 +370,14 @@ check_os_arm_support(void) static void get_cpu_topology(void) { - uint32_t regs[4]; - /* Default. This is correct if L3 is not present or there is only one. */ util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus; #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) /* AMD Zen */ if (util_cpu_caps.x86_cpu_type == 0x17) { + uint32_t regs[4]; + /* Query the L3 cache topology information. */ cpuid_count(0x8000001D, 3, regs); unsigned cache_level = (regs[0] >> 5) & 0x7; |