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authorKeith Whitwell <[email protected]>2006-09-20 14:39:53 +0000
committerKeith Whitwell <[email protected]>2006-09-20 14:39:53 +0000
commit3a5319293c9210ea3c0c9d84604fa0720a96f0e8 (patch)
treedc37e567416f84f21fbb504eea58dc343895cf95
parentd41d29b8bde9bb9c277424a43d0b80838edfe254 (diff)
Broadwater seems to prefer this style of blitting.
-rw-r--r--src/mesa/drivers/dri/i965/intel_blit.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 2191dd585e1..c57618b388b 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -74,9 +74,6 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv,
if (!rect)
{
- /* This is a really crappy way to do wait-for-vblank. I guess
- * it sortof works in the single-application case.
- */
UNLOCK_HARDWARE( intel );
driWaitForVBlank( dPriv, &intel->vbl_seq, intel->vblank_flags, & missed_target );
LOCK_HARDWARE( intel );
@@ -292,7 +289,7 @@ void intelEmitCopyBlit( struct intel_context *intel,
/* Initial y values don't seem to work with negative pitches. If
* we adjust the offsets manually (below), it seems to work fine.
*/
- if (0) {
+ if (1) {
BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS);
OUT_BATCH( CMD );
OUT_BATCH( dst_pitch | BR13 );