r600g,radeonsi: consolidate transfer, cmask, and fmask structures

9 files changed, 94 insertions, 127 deletions

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 42274720df2..cba1dcd620d 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1188,7 +1188,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 	macro_aspect = eg_macro_tile_aspect(macro_aspect);
 	bankw = eg_bank_wh(bankw);
 	bankh = eg_bank_wh(bankh);
-	fmask_bankh = eg_bank_wh(tmp->fmask_bank_height);
+	fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
 
 	/* 128 bit formats require tile type = 1 */
 	if (rscreen->b.chip_class == CAYMAN) {
@@ -1226,7 +1226,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
 			view->skip_mip_address_reloc = true;
 		} else {
 			/* FMASK should be in MIP_ADDRESS for multisample textures */
-			view->tex_resource_words[3] = (tmp->fmask_offset + r600_resource_va(ctx->screen, texture)) >> 8;
+			view->tex_resource_words[3] = (tmp->fmask.offset + r600_resource_va(ctx->screen, texture)) >> 8;
 		}
 	} else if (state->u.tex.last_level && texture->nr_samples <= 1) {
 		view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
@@ -1444,7 +1444,7 @@ void evergreen_init_color_surface(struct r600_context *rctx,
 	macro_aspect = rtex->surface.mtilea;
 	bankw = rtex->surface.bankw;
 	bankh = rtex->surface.bankh;
-	fmask_bankh = rtex->fmask_bank_height;
+	fmask_bankh = rtex->fmask.bank_height;
 	tile_split = eg_tile_split(tile_split);
 	macro_aspect = eg_macro_tile_aspect(macro_aspect);
 	bankw = eg_bank_wh(bankw);
@@ -1555,10 +1555,10 @@ void evergreen_init_color_surface(struct r600_context *rctx,
 		surf->export_16bpc = true;
 	}
 
-	if (rtex->fmask_size) {
+	if (rtex->fmask.size) {
 		color_info |= S_028C70_COMPRESSION(1);
 	}
-	if (rtex->cmask_size) {
+	if (rtex->cmask.size) {
 		color_info |= S_028C70_FAST_CLEAR(1);
 	}
 
@@ -1577,19 +1577,19 @@ void evergreen_init_color_surface(struct r600_context *rctx,
 				      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
 	}
 	surf->cb_color_attrib = color_attrib;
-	if (rtex->fmask_size) {
-		surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
+	if (rtex->fmask.size) {
+		surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
 	} else {
 		surf->cb_color_fmask = surf->cb_color_base;
 	}
-	if (rtex->cmask_size) {
-		uint64_t va = r600_resource_va(rctx->b.b.screen, &rtex->cmask->b.b);
-		surf->cb_color_cmask = (va + rtex->cmask_offset) >> 8;
+	if (rtex->cmask.size) {
+		uint64_t va = r600_resource_va(rctx->b.b.screen, &rtex->cmask_buffer->b.b);
+		surf->cb_color_cmask = (va + rtex->cmask.offset) >> 8;
 	} else {
 		surf->cb_color_cmask = surf->cb_color_base;
 	}
-	surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask_slice_tile_max);
-	surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
+	surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
+	surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask.slice_tile_max);
 
 	surf->color_initialized = true;
 }
@@ -1767,7 +1767,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 			rctx->framebuffer.export_16bpc = false;
 		}
 
-		if (rtex->fmask_size && rtex->cmask_size) {
+		if (rtex->fmask.size && rtex->cmask.size) {
 			rctx->framebuffer.compressed_cb_mask |= 1 << i;
 		}
 	}
@@ -2188,9 +2188,9 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
 						       (struct r600_resource*)cb->base.texture,
 						       RADEON_USAGE_READWRITE);
 		unsigned cmask_reloc = 0;
-		if (tex->cmask && tex->cmask != &tex->resource) {
+		if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
 			cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
-				tex->cmask, RADEON_USAGE_READWRITE);
+				tex->cmask_buffer, RADEON_USAGE_READWRITE);
 		} else {
 			cmask_reloc = reloc;
 		}
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 056897dac73..1a78b976211 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -313,7 +313,7 @@ static void r600_blit_decompress_color(struct pipe_context *ctx,
 
 			r600_blitter_begin(ctx, R600_DECOMPRESS);
 			util_blitter_custom_color(rctx->blitter, cbsurf,
-				rtex->fmask_size ? rctx->custom_blend_decompress : rctx->custom_blend_fastclear);
+				rtex->fmask.size ? rctx->custom_blend_decompress : rctx->custom_blend_fastclear);
 			r600_blitter_end(ctx);
 
 			pipe_surface_reference(&cbsurf, NULL);
@@ -343,7 +343,7 @@ void r600_decompress_color_textures(struct r600_context *rctx,
 		assert(view);
 
 		tex = (struct r600_texture *)view->texture;
-		assert(tex->cmask_size);
+		assert(tex->cmask.size);
 
 		r600_blit_decompress_color(&rctx->b.b, tex,
 					   view->u.tex.first_level, view->u.tex.last_level,
@@ -378,7 +378,7 @@ static bool r600_decompress_subresource(struct pipe_context *ctx,
 						   first_layer, last_layer,
 						   0, u_max_sample(tex));
 		}
-	} else if (rtex->cmask_size) {
+	} else if (rtex->cmask.size) {
 		r600_blit_decompress_color(ctx, rtex, level, level,
 					   first_layer, last_layer);
 	}
@@ -441,16 +441,16 @@ static void evergreen_check_alloc_cmask(struct pipe_context *ctx,
         struct r600_texture *tex = (struct r600_texture *)cbuf->texture;
         struct r600_surface *surf = (struct r600_surface *)cbuf;
 
-        if (tex->cmask)
+        if (tex->cmask_buffer)
                 return;
 
         r600_texture_init_cmask(rctx->screen, tex);
 
         /* update colorbuffer state bits */
-        if (tex->cmask != NULL) {
-                uint64_t va = r600_resource_va(rctx->b.b.screen, &tex->cmask->b.b);
+        if (tex->cmask_buffer != NULL) {
+                uint64_t va = r600_resource_va(rctx->b.b.screen, &tex->cmask_buffer->b.b);
                 surf->cb_color_cmask = va >> 8;
-                surf->cb_color_cmask_slice = S_028C80_TILE_MAX(tex->cmask_slice_tile_max);
+                surf->cb_color_cmask_slice = S_028C80_TILE_MAX(tex->cmask.slice_tile_max);
                 surf->cb_color_info |= S_028C70_FAST_CLEAR(1);
         }
 }
@@ -491,7 +491,7 @@ static bool can_fast_clear_color(struct pipe_context *ctx)
 
 		/* ensure CMASK is enabled */
 		evergreen_check_alloc_cmask(ctx, fb->cbufs[i]);
-		if (tex->cmask_size == 0) {
+		if (tex->cmask.size == 0) {
 			return false;
 		}
 	}
@@ -514,8 +514,8 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 			struct r600_texture *tex = (struct r600_texture *)fb->cbufs[i]->texture;
 
 			evergreen_set_clear_color(fb->cbufs[i], color);
-			r600_clear_buffer(ctx, &tex->cmask->b.b,
-					tex->cmask_offset, tex->cmask_size, 0);
+			r600_clear_buffer(ctx, &tex->cmask_buffer->b.b,
+					tex->cmask.offset, tex->cmask.size, 0);
 			tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
 		}
 
@@ -530,7 +530,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 		/* cannot use fast clear, make sure to disable expansion */
 		for (i = 0; i < fb->nr_cbufs; i++) {
 			struct r600_texture *tex = (struct r600_texture *)fb->cbufs[i]->texture;
-			if (tex->fmask_size == 0)
+			if (tex->fmask.size == 0)
 			    tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
 		}
 	}
@@ -951,7 +951,7 @@ static void r600_flush_resource(struct pipe_context *ctx,
 
 	assert(res->target != PIPE_BUFFER);
 
-	if (!rtex->is_depth && rtex->cmask_size) {
+	if (!rtex->is_depth && rtex->cmask.size) {
 		r600_blit_decompress_color(ctx, rtex, 0, res->last_level,
 					   0, res->array_size - 1);
 	}
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index eba09a4f71d..3714cd7be37 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -664,13 +664,13 @@ void r600_flag_resource_cache_flush(struct r600_context *rctx,
 				       R600_CONTEXT_FLUSH_AND_INV |
 				       R600_CONTEXT_WAIT_3D_IDLE;
 
-			if (tex->cmask_size || tex->fmask_size) {
+			if (tex->cmask.size || tex->fmask.size) {
 				rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
 			}
 			break;
 		}
 
-		if (tex && tex->cmask && tex->cmask != &tex->resource && &tex->cmask->b.b == res) {
+		if (tex && tex->cmask_buffer && tex->cmask_buffer != &tex->resource && &tex->cmask_buffer->b.b == res) {
 			rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META |
 				       R600_CONTEXT_FLUSH_AND_INV |
 				       R600_CONTEXT_WAIT_3D_IDLE;
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 92e57b6d1b4..9896470255f 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -27,18 +27,6 @@
 #include "../radeon/r600_pipe_common.h"
 
 struct r600_screen;
-
-/* flag to indicate a resource is to be used as a transfer so should not be tiled */
-#define R600_RESOURCE_FLAG_TRANSFER		PIPE_RESOURCE_FLAG_DRV_PRIV
-#define R600_RESOURCE_FLAG_FLUSHED_DEPTH	(PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
-#define R600_RESOURCE_FLAG_FORCE_TILING		(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
-
-struct r600_transfer {
-	struct pipe_transfer		transfer;
-	struct r600_resource		*staging;
-	unsigned			offset;
-};
-
 struct compute_memory_item;
 
 struct r600_resource_global {
@@ -60,36 +48,20 @@ struct r600_texture {
 	boolean				is_flushing_texture;
 	struct radeon_surface		surface;
 
-	/* FMASK and CMASK can only be used with MSAA textures for now.
-	 * MSAA textures cannot have mipmaps. */
-	unsigned			fmask_offset, fmask_size, fmask_bank_height;
-	unsigned			fmask_slice_tile_max;
-	unsigned			cmask_offset, cmask_size;
-	unsigned			cmask_slice_tile_max;
+	/* Colorbuffer compression and fast clear. */
+	struct r600_fmask_info		fmask;
+	struct r600_cmask_info		cmask;
 
 	struct r600_resource		*htile;
 	/* use htile only for first level */
 	float				depth_clear;
 
-	struct r600_resource		*cmask;
+	struct r600_resource		*cmask_buffer;
 	unsigned			color_clear_value[2];
 };
 
 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
 
-struct r600_fmask_info {
-	unsigned size;
-	unsigned alignment;
-	unsigned bank_height;
-	unsigned slice_tile_max;
-};
-
-struct r600_cmask_info {
-	unsigned size;
-	unsigned alignment;
-	unsigned slice_tile_max;
-};
-
 struct r600_surface {
 	struct pipe_surface		base;
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 7a7ed7290ff..5411f743a63 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1399,14 +1399,14 @@ static void r600_init_color_surface(struct r600_context *rctx,
 	pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
 				&rtex->resource.b.b);
 
-	if (rtex->cmask_size) {
-		surf->cb_color_cmask = rtex->cmask_offset >> 8;
-		surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
+	if (rtex->cmask.size) {
+		surf->cb_color_cmask = rtex->cmask.offset >> 8;
+		surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
 
-		if (rtex->fmask_size) {
+		if (rtex->fmask.size) {
 			color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
-			surf->cb_color_fmask = rtex->fmask_offset >> 8;
-			surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask_slice_tile_max);
+			surf->cb_color_fmask = rtex->fmask.offset >> 8;
+			surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
 		} else { /* cmask only */
 			color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
 		}
@@ -1611,7 +1611,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 			rctx->framebuffer.export_16bpc = false;
 		}
 
-		if (rtex->fmask_size && rtex->cmask_size) {
+		if (rtex->fmask.size && rtex->cmask.size) {
 			rctx->framebuffer.compressed_cb_mask |= 1 << i;
 		}
 	}
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index a683bc42d36..2297377e089 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -608,7 +608,7 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 				}
 
 				/* Track compressed colorbuffers. */
-				if (rtex->cmask_size) {
+				if (rtex->cmask.size) {
 					dst->views.compressed_colortex_mask |= 1 << i;
 				} else {
 					dst->views.compressed_colortex_mask &= ~(1 << i);
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 8ba41d19efe..b74718045ec 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -301,8 +301,8 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 		pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 
         pipe_resource_reference((struct pipe_resource**)&rtex->htile, NULL);
-	if (rtex->cmask != &rtex->resource) {
-	    pipe_resource_reference((struct pipe_resource**)&rtex->cmask, NULL);
+	if (rtex->cmask_buffer != &rtex->resource) {
+	    pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
 	}
 	pb_reference(&resource->buf, NULL);
 	FREE(rtex);
@@ -371,11 +371,11 @@ static void r600_texture_allocate_fmask(struct r600_screen *rscreen,
 	r600_texture_get_fmask_info(rscreen, rtex,
 				    rtex->resource.b.b.nr_samples, &fmask);
 
-	rtex->fmask_bank_height = fmask.bank_height;
-	rtex->fmask_slice_tile_max = fmask.slice_tile_max;
-	rtex->fmask_offset = align(rtex->size, fmask.alignment);
-	rtex->fmask_size = fmask.size;
-	rtex->size = rtex->fmask_offset + rtex->fmask_size;
+	rtex->fmask.bank_height = fmask.bank_height;
+	rtex->fmask.slice_tile_max = fmask.slice_tile_max;
+	rtex->fmask.offset = align(rtex->size, fmask.alignment);
+	rtex->fmask.size = fmask.size;
+	rtex->size = rtex->fmask.offset + rtex->fmask.size;
 #if 0
 	printf("FMASK width=%u, height=%i, bits=%u, size=%u\n",
 	       fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size);
@@ -422,10 +422,10 @@ static void r600_texture_allocate_cmask(struct r600_screen *rscreen,
 
 	r600_texture_get_cmask_info(rscreen, rtex, &cmask);
 
-	rtex->cmask_slice_tile_max = cmask.slice_tile_max;
-	rtex->cmask_offset = align(rtex->size, cmask.alignment);
-	rtex->cmask_size = cmask.size;
-	rtex->size = rtex->cmask_offset + rtex->cmask_size;
+	rtex->cmask.slice_tile_max = cmask.slice_tile_max;
+	rtex->cmask.offset = align(rtex->size, cmask.alignment);
+	rtex->cmask.size = cmask.size;
+	rtex->size = rtex->cmask.offset + rtex->cmask.size;
 #if 0
 	printf("CMASK: macro tile width = %u, macro tile height = %u, "
 	       "pitch elements = %u, height = %u, slice tile max = %u\n",
@@ -438,17 +438,17 @@ void r600_texture_init_cmask(struct r600_screen *rscreen,
 			     struct r600_texture *rtex) {
     struct r600_cmask_info cmask;
 
-    assert(rtex->cmask_size == 0);
+    assert(rtex->cmask.size == 0);
 
     r600_texture_get_cmask_info(rscreen, rtex, &cmask);
-    rtex->cmask_slice_tile_max = cmask.slice_tile_max;
-    rtex->cmask_offset = 0;
-    rtex->cmask_size = cmask.size;
-    rtex->cmask = (struct r600_resource *)pipe_buffer_create(&rscreen->b.b,
-	    PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, rtex->cmask_size);
-
-    if (rtex->cmask == NULL) {
-	rtex->cmask_size = 0;
+    rtex->cmask.slice_tile_max = cmask.slice_tile_max;
+    rtex->cmask.offset = 0;
+    rtex->cmask.size = cmask.size;
+    rtex->cmask_buffer = (struct r600_resource *)pipe_buffer_create(&rscreen->b.b,
+	    PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, rtex->cmask.size);
+
+    if (rtex->cmask_buffer == NULL) {
+	rtex->cmask.size = 0;
     }
 }
 
@@ -485,15 +485,15 @@ r600_texture_create_object(struct pipe_screen *screen,
 		return NULL;
 	}
 
-	rtex->cmask = NULL;
+	rtex->cmask_buffer = NULL;
 	if (base->nr_samples > 1 && !rtex->is_depth && !buf) {
 		r600_texture_allocate_fmask(rscreen, rtex);
 		r600_texture_allocate_cmask(rscreen, rtex);
-		rtex->cmask = &rtex->resource;
+		rtex->cmask_buffer = &rtex->resource;
 	}
 
 	if (!rtex->is_depth && base->nr_samples > 1 &&
-	    (!rtex->fmask_size || !rtex->cmask_size)) {
+	    (!rtex->fmask.size || !rtex->cmask.size)) {
 		FREE(rtex);
 		return NULL;
 	}
@@ -553,10 +553,10 @@ r600_texture_create_object(struct pipe_screen *screen,
 		resource->domains = RADEON_DOMAIN_VRAM;
 	}
 
-	if (rtex->cmask_size) {
+	if (rtex->cmask.size) {
 		/* Initialize the cmask to 0xCC (= compressed state). */
-		r600_screen_clear_buffer(rscreen, &rtex->cmask->b.b,
-					 rtex->cmask_offset, rtex->cmask_size, 0xCC);
+		r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
+					 rtex->cmask.offset, rtex->cmask.size, 0xCC);
 	}
 
 	if (rscreen->debug_flags & DBG_VM) {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index b5c32bb75e7..0bd696a8818 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -38,6 +38,10 @@
 #include "util/u_suballoc.h"
 #include "util/u_transfer.h"
 
+#define R600_RESOURCE_FLAG_TRANSFER		(PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
+#define R600_RESOURCE_FLAG_FLUSHED_DEPTH	(PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
+#define R600_RESOURCE_FLAG_FORCE_TILING		(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+
 /* read caches */
 #define R600_CONTEXT_INV_VERTEX_CACHE		(1 << 0)
 #define R600_CONTEXT_INV_TEX_CACHE		(1 << 1)
@@ -78,6 +82,29 @@ struct r600_resource {
 	struct util_range		valid_buffer_range;
 };
 
+struct r600_transfer {
+	struct pipe_transfer		transfer;
+	struct r600_resource		*staging;
+	unsigned			offset;
+};
+
+struct r600_fmask_info {
+	unsigned offset;
+	unsigned size;
+	unsigned alignment;
+	unsigned pitch;
+	unsigned bank_height;
+	unsigned slice_tile_max;
+	unsigned tile_mode_index;
+};
+
+struct r600_cmask_info {
+	unsigned offset;
+	unsigned size;
+	unsigned alignment;
+	unsigned slice_tile_max;
+};
+
 struct r600_common_screen {
 	struct pipe_screen		b;
 	struct radeon_winsys		*ws;
diff --git a/src/gallium/drivers/radeonsi/r600_resource.h b/src/gallium/drivers/radeonsi/r600_resource.h
index 185ae25205b..ab9ddbe010a 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -25,38 +25,6 @@
 
 #include "util/u_transfer.h"
 
-/* flag to indicate a resource is to be used as a transfer so should not be tiled */
-#define R600_RESOURCE_FLAG_TRANSFER		PIPE_RESOURCE_FLAG_DRV_PRIV
-#define R600_RESOURCE_FLAG_FLUSHED_DEPTH	(PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
-#define R600_RESOURCE_FLAG_FORCE_TILING		(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
-
-/* Texture transfer. */
-struct r600_transfer {
-	/* Base class. */
-	struct pipe_transfer		transfer;
-	/* Buffer transfer. */
-	struct pipe_transfer		*buffer_transfer;
-	unsigned			offset;
-	struct r600_resource		*staging;
-};
-
-struct r600_fmask_info {
-	unsigned offset;
-	unsigned size;
-	unsigned alignment;
-	unsigned pitch;
-	unsigned bank_height;
-	unsigned slice_tile_max;
-	unsigned tile_mode_index;
-};
-
-struct r600_cmask_info {
-	unsigned offset;
-	unsigned size;
-	unsigned alignment;
-	unsigned slice_tile_max;
-};
-
 struct r600_texture {
 	struct r600_resource		resource;