diff options
author | Jose Maria Casanova Crespo <[email protected]> | 2017-07-01 07:58:26 +0200 |
---|---|---|
committer | Jose Maria Casanova Crespo <[email protected]> | 2017-12-06 08:57:18 +0100 |
commit | 1f440d00d2b6ae6f74fb850ea5acec1f1b5efa58 (patch) | |
tree | 46460eeeeeeefe82036e98926071b06ba92e441e | |
parent | 2af63683bc61e1efb8f634697770d314ef07c882 (diff) |
nir: Handle fp16 rounding modes at nir_type_conversion_op
nir_type_conversion enables new operations to handle rounding modes to
convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne
and nir_op_f2f16_rtz.
The undefined behaviour doesn't has any effect and uses the original
nir_op_f2f16 operation.
v2: Indentation fixed (Jason Ekstrand)
v3: Use explicit case for undefined rounding and assert if
rounding mode is used for non 16-bit float conversions
(Jason Ekstrand)
Reviewed-by: Jason Ekstrand <[email protected]>
-rw-r--r-- | src/compiler/glsl/glsl_to_nir.cpp | 3 | ||||
-rw-r--r-- | src/compiler/nir/nir.h | 3 | ||||
-rw-r--r-- | src/compiler/nir/nir_opcodes.py | 11 | ||||
-rw-r--r-- | src/compiler/nir/nir_opcodes_c.py | 15 | ||||
-rw-r--r-- | src/compiler/spirv/vtn_alu.c | 2 |
5 files changed, 28 insertions, 6 deletions
diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 67f15977ee5..0493410aebe 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -1575,7 +1575,8 @@ nir_visitor::visit(ir_expression *ir) case ir_unop_u642i64: { nir_alu_type src_type = nir_get_nir_type_for_glsl_base_type(types[0]); nir_alu_type dst_type = nir_get_nir_type_for_glsl_base_type(out_type); - result = nir_build_alu(&b, nir_type_conversion_op(src_type, dst_type), + result = nir_build_alu(&b, nir_type_conversion_op(src_type, dst_type, + nir_rounding_mode_undef), srcs[0], NULL, NULL, NULL); /* b2i and b2f don't have fixed bit-size versions so the builder will * just assume 32 and we have to fix it up here. diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 1e0dee91192..25c36c66ef9 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -761,7 +761,8 @@ nir_get_nir_type_for_glsl_type(const struct glsl_type *type) return nir_get_nir_type_for_glsl_base_type(glsl_get_base_type(type)); } -nir_op nir_type_conversion_op(nir_alu_type src, nir_alu_type dst); +nir_op nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, + nir_rounding_mode rnd); typedef enum { NIR_OP_IS_COMMUTATIVE = (1 << 0), diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 28a04672285..ac7333fe781 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -179,8 +179,15 @@ for src_t in [tint, tuint, tfloat]: else: bit_sizes = [8, 16, 32, 64] for bit_size in bit_sizes: - unop_convert("{0}2{1}{2}".format(src_t[0], dst_t[0], bit_size), - dst_t + str(bit_size), src_t, "src0") + if bit_size == 16 and dst_t == tfloat and src_t == tfloat: + rnd_modes = ['rtne', 'rtz', 'undef'] + for rnd_mode in rnd_modes: + unop_convert("{0}2{1}{2}_{3}".format(src_t[0], dst_t[0], + bit_size, rnd_mode), + dst_t + str(bit_size), src_t, "src0") + else: + unop_convert("{0}2{1}{2}".format(src_t[0], dst_t[0], bit_size), + dst_t + str(bit_size), src_t, "src0") # We'll hand-code the to/from bool conversion opcodes. Because bool doesn't # have multiple bit-sizes, we can always infer the size from the other type. diff --git a/src/compiler/nir/nir_opcodes_c.py b/src/compiler/nir/nir_opcodes_c.py index 02bb4738ed8..c19185534af 100644 --- a/src/compiler/nir/nir_opcodes_c.py +++ b/src/compiler/nir/nir_opcodes_c.py @@ -30,7 +30,7 @@ template = Template(""" #include "nir.h" nir_op -nir_type_conversion_op(nir_alu_type src, nir_alu_type dst) +nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd) { nir_alu_type src_base = (nir_alu_type) nir_alu_type_get_base_type(src); nir_alu_type dst_base = (nir_alu_type) nir_alu_type_get_base_type(dst); @@ -64,7 +64,20 @@ nir_type_conversion_op(nir_alu_type src, nir_alu_type dst) switch (dst_bit_size) { % for dst_bits in [16, 32, 64]: case ${dst_bits}: +% if src_t == 'float' and dst_t == 'float' and dst_bits == 16: + switch(rnd) { +% for rnd_t in ['rtne', 'rtz', 'undef']: + case nir_rounding_mode_${rnd_t}: + return ${'nir_op_{0}2{1}{2}_{3}'.format(src_t[0], dst_t[0], + dst_bits, rnd_t)}; +% endfor + default: + unreachable("Invalid 16-bit nir rounding mode"); + } +% else: + assert(rnd == nir_rounding_mode_undef); return ${'nir_op_{0}2{1}{2}'.format(src_t[0], dst_t[0], dst_bits)}; +% endif % endfor default: unreachable("Invalid nir alu bit size"); diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 7653b8acfa1..fa4dbfecddd 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -356,7 +356,7 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, case SpvOpConvertUToF: case SpvOpSConvert: case SpvOpFConvert: - return nir_type_conversion_op(src, dst); + return nir_type_conversion_op(src, dst, nir_rounding_mode_undef); /* Derivatives: */ case SpvOpDPdx: return nir_op_fddx; |