diff options
| author | Samuel Pitoiset <[email protected]> | 2020-01-16 14:37:11 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-20 16:24:55 +0000 |
| commit | 1b5bb204d9724e166b33dc03bb187499088f278d (patch) | |
| tree | 22bd12b360bffd22b5c0346e3e98a406d45b654a | |
| parent | b8abfafe8690847dc09bb63a5674dc2e2228a56a (diff) | |
aco: do not use the vec3 variant for stores on GFX6
GFX6 only supports vec3 with load/store format.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-By: Timur Kristóf <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 6d6d806a2d0..250f7011b04 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -4501,7 +4501,8 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr) while (writemask) { int start, count; u_bit_scan_consecutive_range(&writemask, &start, &count); - if (count == 3 && smem) { + if (count == 3 && (smem || ctx->options->chip_class == GFX6)) { + /* GFX6 doesn't support storing vec3, split it. */ writemask |= 1u << (start + 2); count = 2; } @@ -4551,7 +4552,7 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr) case 12: vmem_op = aco_opcode::buffer_store_dwordx3; smem_op = aco_opcode::last_opcode; - assert(!smem); + assert(!smem && ctx->options->chip_class > GFX6); break; case 16: vmem_op = aco_opcode::buffer_store_dwordx4; |