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authorDave Airlie <[email protected]>2017-08-15 15:18:04 +1000
committerDave Airlie <[email protected]>2017-08-16 05:54:03 +1000
commitfc600eb98d5846fe59f4a79ed1c7ad2a0667e927 (patch)
treeeabb97e4809d64d0b23324b0f7e0078fcff58eda
parent5247b311e9b348fedd74980a34c4b6542d85b07b (diff)
radv/gfx9: remove some leftover gfx6 descriptor setup.
We set this later in the non-gfx9 path, just remove these bits from here. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
-rw-r--r--src/amd/vulkan/radv_image.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c0064c0a170..8d3ff1a515e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -204,7 +204,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
{
uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0;
uint64_t va = gpu_address;
- unsigned pitch = base_level_info->nblk_x * block_width;
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
uint64_t meta_va = 0;
if (chip_class >= GFX9) {
@@ -221,9 +220,6 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
state[0] |= image->surface.tile_swizzle;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
- state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
- is_stencil));
- state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
if (chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;