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authorJason Ekstrand <[email protected]>2017-06-14 18:54:29 -0700
committerKenneth Graunke <[email protected]>2017-07-26 14:43:01 -0700
commitf6e478c213c30203e9623d5657fd3789cf6368f3 (patch)
tree78728ed75c939dc6f32d693bd7146e8f7958b9a4
parent6db193701e7d03e0eadd54fc3e1b3d75719bc4ae (diff)
i965/clear: Don't perform redundant depth clears
We already have this little optimization for color clears. Now that we're actually tracking whether or not a slice has any fast-clear blocks, it's easy enough to add for depth clears too. Improves performance of GFXBench 4 TRex at 1920x1080 by: - Skylake GT4: 0.905932% +/- 0.0620197% (n = 30) - Apollolake: 0.382434% +/- 0.1134730% (n = 25) v2: (by Ken) Rebase and drop intel_mipmap_tree.c changes, as they're no longer necessary (other patches already landed to do that part) Reviewed-by: Kenneth Graunke <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c34
1 files changed, 31 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 0429b3b6f51..5eb24237927 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -204,9 +204,37 @@ brw_fast_clear_depth(struct gl_context *ctx)
mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
}
- intel_hiz_exec(brw, mt, depth_irb->mt_level,
- depth_irb->mt_layer, num_layers,
- BLORP_HIZ_OP_DEPTH_CLEAR);
+ bool need_clear = false;
+ for (unsigned a = 0; a < num_layers; a++) {
+ enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
+
+ if (aux_state != ISL_AUX_STATE_CLEAR) {
+ need_clear = true;
+ break;
+ }
+ }
+
+ if (!need_clear) {
+ /* If all of the layers we intend to clear are already in the clear
+ * state then simply updating the miptree fast clear value is sufficient
+ * to change their clear value.
+ */
+ return true;
+ }
+
+ for (unsigned a = 0; a < num_layers; a++) {
+ enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
+
+ if (aux_state != ISL_AUX_STATE_CLEAR) {
+ intel_hiz_exec(brw, mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a, 1,
+ BLORP_HIZ_OP_DEPTH_CLEAR);
+ }
+ }
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
* buffer.