diff options
| author | Ilia Mirkin <[email protected]> | 2019-08-06 23:02:53 -0400 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2019-08-07 22:32:02 -0400 |
| commit | f6af10434087397428d5b2f6d39ff559f70c7c0f (patch) | |
| tree | 5d454d48ca0e9444bd8f08033efc5b50ea294a8e | |
| parent | a2bb7b26a1c4ed1c00c9d81bcd0318ff0acb141a (diff) | |
nvc0: add support for ATOMC_WRAP TGSI operations
Signed-off-by: Ilia Mirkin <[email protected]>
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 10 | ||||
| -rw-r--r-- | src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index 2dd13e70d0e..c3e3cf2dff5 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -606,6 +606,8 @@ nv50_ir::DataType Instruction::inferSrcType() const case TGSI_OPCODE_ATOMXOR: case TGSI_OPCODE_ATOMUMIN: case TGSI_OPCODE_ATOMUMAX: + case TGSI_OPCODE_ATOMDEC_WRAP: + case TGSI_OPCODE_ATOMINC_WRAP: case TGSI_OPCODE_UBFE: case TGSI_OPCODE_UMSB: case TGSI_OPCODE_UP2H: @@ -969,6 +971,8 @@ static nv50_ir::operation translateOpcode(uint opcode) NV50_IR_OPCODE_CASE(ATOMIMIN, ATOM); NV50_IR_OPCODE_CASE(ATOMIMAX, ATOM); NV50_IR_OPCODE_CASE(ATOMFADD, ATOM); + NV50_IR_OPCODE_CASE(ATOMDEC_WRAP, ATOM); + NV50_IR_OPCODE_CASE(ATOMINC_WRAP, ATOM); NV50_IR_OPCODE_CASE(TEX2, TEX); NV50_IR_OPCODE_CASE(TXB2, TXB); @@ -1012,6 +1016,8 @@ static uint16_t opcodeToSubOp(uint opcode) case TGSI_OPCODE_ATOMUMAX: return NV50_IR_SUBOP_ATOM_MAX; case TGSI_OPCODE_ATOMIMAX: return NV50_IR_SUBOP_ATOM_MAX; case TGSI_OPCODE_ATOMFADD: return NV50_IR_SUBOP_ATOM_ADD; + case TGSI_OPCODE_ATOMDEC_WRAP: return NV50_IR_SUBOP_ATOM_DEC; + case TGSI_OPCODE_ATOMINC_WRAP: return NV50_IR_SUBOP_ATOM_INC; case TGSI_OPCODE_IMUL_HI: case TGSI_OPCODE_UMUL_HI: return NV50_IR_SUBOP_MUL_HIGH; @@ -1628,6 +1634,8 @@ bool Source::scanInstruction(const struct tgsi_full_instruction *inst) case TGSI_OPCODE_ATOMUMAX: case TGSI_OPCODE_ATOMIMAX: case TGSI_OPCODE_ATOMFADD: + case TGSI_OPCODE_ATOMDEC_WRAP: + case TGSI_OPCODE_ATOMINC_WRAP: case TGSI_OPCODE_LOAD: info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ? 0x1 : 0x2; @@ -3779,6 +3787,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) case TGSI_OPCODE_ATOMUMAX: case TGSI_OPCODE_ATOMIMAX: case TGSI_OPCODE_ATOMFADD: + case TGSI_OPCODE_ATOMDEC_WRAP: + case TGSI_OPCODE_ATOMINC_WRAP: handleATOM(dst0, dstTy, tgsi::opcodeToSubOp(tgsi.getOpcode())); break; case TGSI_OPCODE_RESQ: diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 8a9d3c4d0bd..b1e12432e14 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -280,6 +280,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL: case PIPE_CAP_TGSI_DIV: + case PIPE_CAP_TGSI_ATOMINC_WRAP: return 1; case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0; @@ -364,7 +365,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED: case PIPE_CAP_FBFETCH_COHERENT: case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS: - case PIPE_CAP_TGSI_ATOMINC_WRAP: return 0; case PIPE_CAP_VENDOR_ID: |