i965/miptree/gen7+: Use isl for hiz layouts

v2: Use better assert by checking isl_surf_get_hiz_surf()

Reviewed-by: Jason Ekstrand <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>

7 files changed, 33 insertions, 245 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 897215e0bd2..cec12bf4db6 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -167,7 +167,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
 
    struct isl_surf *aux_surf;
    if (brw->gen == 6 && mt->hiz_buf) {
-      aux_surf = &mt->hiz_buf->aux_base.surf;
+      aux_surf = &mt->hiz_buf->surf;
    } else if (mt->mcs_buf) {
       aux_surf = &mt->mcs_buf->surf;
    } else {
@@ -212,8 +212,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
       } else {
          assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
 
-         surf->aux_addr.buffer = mt->hiz_buf->aux_base.bo;
-         surf->aux_addr.offset = mt->hiz_buf->aux_base.offset;
+         surf->aux_addr.buffer = mt->hiz_buf->bo;
+         surf->aux_addr.offset = mt->hiz_buf->offset;
       }
    } else {
       surf->aux_addr = (struct blorp_address) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 1b4ef0900db..43c2aa49209 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -154,8 +154,8 @@ brw_emit_surface_state(struct brw_context *brw,
          intel_miptree_get_aux_isl_surf(brw, mt, aux_usage, &aux_surf_s);
          aux_surf = &aux_surf_s;
 
-         aux_bo = mt->hiz_buf->aux_base.bo;
-         aux_offset = mt->hiz_buf->aux_base.bo->offset64;
+         aux_bo = mt->hiz_buf->bo;
+         aux_offset = mt->hiz_buf->bo->offset64;
       }
 
       /* We only really need a clear color if we also have an auxiliary
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 0f5e4d32018..cd681cbc1f0 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -167,13 +167,13 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
          assert(depth_mt);
 
          uint32_t offset;
-         isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->aux_base.surf,
+         isl_surf_get_image_offset_B_tile_sa(&depth_mt->hiz_buf->surf,
                                              lod, 0, 0, &offset, NULL, NULL);
 
 	 BEGIN_BATCH(3);
 	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-	 OUT_BATCH(depth_mt->hiz_buf->aux_base.surf.row_pitch - 1);
-	 OUT_RELOC(depth_mt->hiz_buf->aux_base.bo,
+	 OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
+	 OUT_RELOC(depth_mt->hiz_buf->bo,
 		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		   offset);
 	 ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 16b08ed8687..d417f7c2994 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -146,13 +146,12 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       ADVANCE_BATCH();
    } else {
       assert(depth_mt);
-      struct intel_miptree_hiz_buffer *hiz_buf = depth_mt->hiz_buf;
 
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_buf->aux_base.pitch - 1));
-      OUT_RELOC(hiz_buf->aux_base.bo,
+                (depth_mt->hiz_buf->pitch - 1));
+      OUT_RELOC(depth_mt->hiz_buf->bo,
                 I915_GEM_DOMAIN_RENDER,
                 I915_GEM_DOMAIN_RENDER,
                 0);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 39a786c968f..c961c8d7aed 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -93,10 +93,10 @@ emit_depth_packets(struct brw_context *brw,
       assert(depth_mt);
       BEGIN_BATCH(5);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
-      OUT_BATCH((depth_mt->hiz_buf->aux_base.pitch - 1) | mocs_wb << 25);
-      OUT_RELOC64(depth_mt->hiz_buf->aux_base.bo,
+      OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
+      OUT_RELOC64(depth_mt->hiz_buf->bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-      OUT_BATCH(depth_mt->hiz_buf->aux_base.qpitch >> 2);
+      OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
       ADVANCE_BATCH();
    }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 42fbed34b51..ca202c4e66e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1073,14 +1073,14 @@ intel_miptree_reference(struct intel_mipmap_tree **dst,
 }
 
 static void
-intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer *hiz_buf)
+intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer *aux_buf)
 {
-   if (hiz_buf == NULL)
+   if (aux_buf == NULL)
       return;
 
-   brw_bo_unreference(hiz_buf->aux_base.bo);
+   brw_bo_unreference(aux_buf->bo);
 
-   free(hiz_buf);
+   free(aux_buf);
 }
 
 void
@@ -1098,11 +1098,8 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
       brw_bo_unreference((*mt)->bo);
       intel_miptree_release(&(*mt)->stencil_mt);
       intel_miptree_release(&(*mt)->r8stencil_mt);
-      intel_miptree_hiz_buffer_free((*mt)->hiz_buf);
-      if ((*mt)->mcs_buf) {
-         brw_bo_unreference((*mt)->mcs_buf->bo);
-         free((*mt)->mcs_buf);
-      }
+      intel_miptree_aux_buffer_free((*mt)->hiz_buf);
+      intel_miptree_aux_buffer_free((*mt)->mcs_buf);
       free_aux_state_map((*mt)->aux_state);
 
       intel_miptree_release(&(*mt)->plane[0]);
@@ -1794,208 +1791,6 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
    return true;
 }
 
-
-/**
- * Helper for intel_miptree_alloc_hiz() that determines the required hiz
- * buffer dimensions and allocates a bo for the hiz buffer.
- */
-static struct intel_miptree_hiz_buffer *
-intel_gen7_hiz_buf_create(struct brw_context *brw,
-                          struct intel_mipmap_tree *mt)
-{
-   unsigned z_width = mt->logical_width0;
-   unsigned z_height = mt->logical_height0;
-   const unsigned z_depth = MAX2(mt->logical_depth0, 1);
-   unsigned hz_width, hz_height;
-   struct intel_miptree_hiz_buffer *buf = calloc(sizeof(*buf), 1);
-
-   if (!buf)
-      return NULL;
-
-   /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
-    * adjustments required for Z_Height and Z_Width based on multisampling.
-    */
-   switch (mt->num_samples) {
-   case 0:
-   case 1:
-      break;
-   case 2:
-   case 4:
-      z_width *= 2;
-      z_height *= 2;
-      break;
-   case 8:
-      z_width *= 4;
-      z_height *= 2;
-      break;
-   default:
-      unreachable("unsupported sample count");
-   }
-
-   const unsigned vertical_align = 8; /* 'j' in the docs */
-   const unsigned H0 = z_height;
-   const unsigned h0 = ALIGN(H0, vertical_align);
-   const unsigned h1 = ALIGN(minify(H0, 1), vertical_align);
-   const unsigned Z0 = z_depth;
-
-   /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
-   hz_width = ALIGN(z_width, 16);
-
-   if (mt->target == GL_TEXTURE_3D) {
-      unsigned H_i = H0;
-      unsigned Z_i = Z0;
-      hz_height = 0;
-      for (unsigned level = mt->first_level; level <= mt->last_level; ++level) {
-         unsigned h_i = ALIGN(H_i, vertical_align);
-         /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
-         hz_height += h_i * Z_i;
-         H_i = minify(H_i, 1);
-         Z_i = minify(Z_i, 1);
-      }
-      /* HZ_Height =
-       *    (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
-       */
-      hz_height = DIV_ROUND_UP(hz_height, 2);
-   } else {
-      const unsigned hz_qpitch = h0 + h1 + (12 * vertical_align);
-      /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
-      hz_height = DIV_ROUND_UP(hz_qpitch * Z0, 2 * 8) * 8;
-   }
-
-   buf->aux_base.bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "hiz",
-                                            hz_width, hz_height, 1,
-                                            I915_TILING_Y, &buf->aux_base.pitch,
-                                            BO_ALLOC_FOR_RENDER);
-   if (!buf->aux_base.bo) {
-      free(buf);
-      return NULL;
-   }
-
-   buf->aux_base.size = hz_width * hz_height;
-
-   return buf;
-}
-
-
-/**
- * Helper for intel_miptree_alloc_hiz() that determines the required hiz
- * buffer dimensions and allocates a bo for the hiz buffer.
- */
-static struct intel_miptree_hiz_buffer *
-intel_gen8_hiz_buf_create(struct brw_context *brw,
-                          struct intel_mipmap_tree *mt)
-{
-   unsigned z_width = mt->logical_width0;
-   unsigned z_height = mt->logical_height0;
-   const unsigned z_depth = MAX2(mt->logical_depth0, 1);
-   unsigned hz_width, hz_height;
-   struct intel_miptree_hiz_buffer *buf = calloc(sizeof(*buf), 1);
-
-   if (!buf)
-      return NULL;
-
-   /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
-    * adjustments required for Z_Height and Z_Width based on multisampling.
-    */
-   if (brw->gen < 9) {
-      switch (mt->num_samples) {
-      case 0:
-      case 1:
-         break;
-      case 2:
-      case 4:
-         z_width *= 2;
-         z_height *= 2;
-         break;
-      case 8:
-         z_width *= 4;
-         z_height *= 2;
-         break;
-      default:
-         unreachable("unsupported sample count");
-      }
-   }
-
-   const unsigned vertical_align = 8; /* 'j' in the docs */
-   const unsigned H0 = z_height;
-   const unsigned h0 = ALIGN(H0, vertical_align);
-   const unsigned h1 = ALIGN(minify(H0, 1), vertical_align);
-   const unsigned Z0 = z_depth;
-
-   /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
-   hz_width = ALIGN(z_width, 16);
-
-   unsigned H_i = H0;
-   unsigned Z_i = Z0;
-   unsigned sum_h_i = 0;
-   unsigned hz_height_3d_sum = 0;
-   for (unsigned level = mt->first_level; level <= mt->last_level; ++level) {
-      unsigned i = level - mt->first_level;
-      unsigned h_i = ALIGN(H_i, vertical_align);
-      /* sum(i=2 to m; h_i) */
-      if (i >= 2) {
-         sum_h_i += h_i;
-      }
-      /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
-      hz_height_3d_sum += h_i * Z_i;
-      H_i = minify(H_i, 1);
-      Z_i = minify(Z_i, 1);
-   }
-   /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
-   buf->aux_base.qpitch = h0 + MAX2(h1, sum_h_i);
-
-   if (mt->target == GL_TEXTURE_3D) {
-      /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
-      hz_height = DIV_ROUND_UP(hz_height_3d_sum, 2);
-   } else {
-      /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
-      hz_height = DIV_ROUND_UP(buf->aux_base.qpitch, 2 * 8) * 8 * Z0;
-   }
-
-   buf->aux_base.bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "hiz",
-                                            hz_width, hz_height, 1,
-                                            I915_TILING_Y, &buf->aux_base.pitch,
-                                            BO_ALLOC_FOR_RENDER);
-   if (!buf->aux_base.bo) {
-      free(buf);
-      return NULL;
-   }
-
-   buf->aux_base.size = hz_width * hz_height;
-
-   return buf;
-}
-
-
-static struct intel_miptree_hiz_buffer *
-intel_hiz_miptree_buf_create(struct brw_context *brw,
-                             struct intel_mipmap_tree *mt)
-{
-   struct intel_miptree_hiz_buffer *buf = calloc(sizeof(*buf), 1);
-   if (!buf)
-      return NULL;
-
-   struct isl_surf temp_main_surf;
-   intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
-
-   if (!isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf,
-                              &buf->aux_base.surf)) {
-      free(buf);
-      return NULL;
-   }
-
-   struct isl_surf *surf = &buf->aux_base.surf;
-   buf->aux_base.bo = brw_bo_alloc_tiled(brw->bufmgr, "hiz", surf->size,
-                                         I915_TILING_Y, surf->row_pitch,
-                                         BO_ALLOC_FOR_RENDER);
-   if (!buf->aux_base.bo) {
-      free(buf);
-      return NULL;
-   }
-
-   return buf;
-}
-
 bool
 intel_miptree_wants_hiz_buffer(struct brw_context *brw,
                                struct intel_mipmap_tree *mt)
@@ -2033,13 +1828,16 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
    if (!aux_state)
       return false;
 
-   if (brw->gen == 7) {
-      mt->hiz_buf = intel_gen7_hiz_buf_create(brw, mt);
-   } else if (brw->gen >= 8) {
-      mt->hiz_buf = intel_gen8_hiz_buf_create(brw, mt);
-   } else {
-      mt->hiz_buf = intel_hiz_miptree_buf_create(brw, mt);
-   }
+   struct isl_surf temp_main_surf;
+   struct isl_surf temp_hiz_surf;
+
+   intel_miptree_get_isl_surf(brw, mt, &temp_main_surf);
+   assert(isl_surf_get_hiz_surf(&brw->isl_dev, &temp_main_surf,
+                                &temp_hiz_surf));
+
+   const uint32_t alloc_flags = BO_ALLOC_FOR_RENDER;
+   mt->hiz_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
+                                        &temp_hiz_surf, alloc_flags, mt);
 
    if (!mt->hiz_buf) {
       free(aux_state);
@@ -2810,7 +2608,7 @@ intel_miptree_make_shareable(struct brw_context *brw,
 
    if (mt->hiz_buf) {
       mt->aux_disable |= INTEL_AUX_DISABLE_HIZ;
-      intel_miptree_hiz_buffer_free(mt->hiz_buf);
+      intel_miptree_aux_buffer_free(mt->hiz_buf);
       mt->hiz_buf = NULL;
 
       for (uint32_t l = mt->first_level; l <= mt->last_level; ++l) {
@@ -3946,8 +3744,8 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw,
       aux_pitch = mt->mcs_buf->pitch;
       aux_qpitch = mt->mcs_buf->qpitch;
    } else if (mt->hiz_buf) {
-      aux_pitch = mt->hiz_buf->aux_base.pitch;
-      aux_qpitch = mt->hiz_buf->aux_base.qpitch;
+      aux_pitch = mt->hiz_buf->surf.row_pitch;
+      aux_qpitch = mt->hiz_buf->surf.array_pitch_el_rows;
    } else {
       return;
    }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 410ed7ef716..0a53319a0d6 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -354,15 +354,6 @@ struct intel_miptree_aux_buffer
     */
    uint32_t qpitch;
 };
-/**
- * The HiZ buffer requires extra attributes on earlier GENs. This is easily
- * contained within an intel_mipmap_tree. To make sure we do not abuse this, we
- * keep the hiz datastructure separate.
- */
-struct intel_miptree_hiz_buffer
-{
-   struct intel_miptree_aux_buffer aux_base;
-};
 
 struct intel_mipmap_tree
 {
@@ -572,7 +563,7 @@ struct intel_mipmap_tree
     * To determine if hiz is enabled, do not check this pointer. Instead, use
     * intel_miptree_slice_has_hiz().
     */
-   struct intel_miptree_hiz_buffer *hiz_buf;
+   struct intel_miptree_aux_buffer *hiz_buf;
 
    /**
     * \brief Maps miptree slices to their current aux state