diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2019-08-21 10:27:05 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-08-21 09:51:47 +0000 |
| commit | e04761d0f9b5b10eed01bc4c2893070a31aa35cf (patch) | |
| tree | 4a28969a096f3e8cc8c7444db6cfc59e374a921c | |
| parent | 2e763f7c87cefbb0c2c8d692e8e1584f89b4c747 (diff) | |
radv: Emit VGT_GS_ONCHIP_CNTL for tess on GFX10.
Otherwise hangs are possible. This register was already set for
GS and NGG.
Fixes: 5eaed7ecfce "radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14"
Reviewed-by: Samuel Pitoiset <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 64bd0d64401..4e9e9e9c9cd 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3812,6 +3812,14 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, else radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, tess->ls_hs_config); + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && + !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) { + radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, + S_028A44_ES_VERTS_PER_SUBGRP(250) | + S_028A44_GS_PRIMS_PER_SUBGRP(126) | + S_028A44_GS_INST_PRIMS_IN_SUBGRP(126)); + } } static void |