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authorNicolai Hähnle <[email protected]>2019-04-01 15:58:31 +0200
committerMarek Olšák <[email protected]>2019-07-03 15:51:13 -0400
commitbcd2d2e1942ab7158dd46a5223130498cb0a8f44 (patch)
treeca89a578a428b4be8cc6becb0c39823dd892007b
parent22b85bfc02ca474b4cc2e5a27f4da052f5539492 (diff)
radeonsi/gfx10: enable the workaround for unaligned vertex fetch
Yes, really. Note that non-format buffer loads are unaffected and work just fine with unaligned pointers (as long as SH_MEM_CONFIG is setup correctly, which amdgpu ensures). Fixes e.g. KHR-GL45.vertex_attrib_64bit.vao Acked-by: Bas Nieuwenhuizen <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 35167f31fb1..68ba7d6403e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4970,7 +4970,9 @@ static void *si_create_vertex_elements(struct pipe_context *ctx,
* into account would complicate the fast path (where everything
* is nicely aligned).
*/
- bool check_alignment = log_hw_load_size >= 1 && sscreen->info.chip_class == GFX6;
+ bool check_alignment =
+ log_hw_load_size >= 1 &&
+ (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
bool opencode = sscreen->options.vs_fetch_always_opencode;
if (check_alignment &&