radeonsi: emit clip registers only if VS, GS, or rasterizer is changed

Reviewed-by: Michel Dänzer <[email protected]>

5 files changed, 39 insertions, 32 deletions

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index 2bf1209ae26..f597218cf67 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -145,6 +145,7 @@ void si_begin_new_cs(struct si_context *ctx)
 	si_pm4_emit(ctx, ctx->queued.named.init);
 	ctx->emitted.named.init = ctx->queued.named.init;
 
+	ctx->clip_regs.dirty = true;
 	ctx->framebuffer.atom.dirty = true;
 	ctx->msaa_config.dirty = true;
 	ctx->db_render_state.dirty = true;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 63995f083c1..15ca9a559e5 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -38,7 +38,7 @@
 #define SI_TRACE_CS_DWORDS		6
 
 #define SI_MAX_DRAW_CS_DWORDS \
-	(/*clip + derived prim state:*/ 12 + /*draw regs:*/ 16 + /*draw packets:*/ 31)
+	(/*derived prim state:*/ 6 + /*draw regs:*/ 16 + /*draw packets:*/ 31)
 
 struct si_compute;
 
@@ -109,6 +109,7 @@ struct si_context {
 			struct r600_atom *framebuffer;
 			struct r600_atom *db_render_state;
 			struct r600_atom *msaa_config;
+			struct r600_atom *clip_regs;
 		} s;
 		struct r600_atom *array[0];
 	} atoms;
@@ -133,6 +134,7 @@ struct si_context {
 	struct r600_resource		*border_color_table;
 	unsigned			border_color_offset;
 
+	struct r600_atom		clip_regs;
 	struct r600_atom		msaa_config;
 	int				ps_iter_samples;
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 6eb00062e54..59166fa7c0c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -450,6 +450,36 @@ static void si_set_clip_state(struct pipe_context *ctx,
 	si_pm4_set_state(sctx, clip, pm4);
 }
 
+#define SIX_BITS 0x3F
+
+static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
+{
+	struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+	struct tgsi_shader_info *info = si_get_vs_info(sctx);
+	struct si_shader *vs = si_get_vs_state(sctx);
+	unsigned window_space =
+	   vs->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+	unsigned clipdist_mask =
+		info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
+
+	r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
+		S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
+		S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
+		S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
+		S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
+		S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
+		S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
+					    info->writes_edgeflag ||
+					    info->writes_layer) |
+		(sctx->queued.named.rasterizer->clip_plane_enable &
+		 clipdist_mask));
+	r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
+		sctx->queued.named.rasterizer->pa_cl_clip_cntl |
+		(clipdist_mask ? 0 :
+		 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
+		S_028810_CLIP_DISABLE(window_space));
+}
+
 static void si_set_scissor_states(struct pipe_context *ctx,
                                   unsigned start_slot,
                                   unsigned num_scissors,
@@ -680,6 +710,8 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
 
 	si_pm4_bind_state(sctx, rasterizer, rs);
 	si_update_fb_rs_state(sctx);
+
+	sctx->clip_regs.dirty = true;
 }
 
 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
@@ -2738,6 +2770,7 @@ void si_init_state_functions(struct si_context *sctx)
 {
 	si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
 	si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
+	si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
 
 	sctx->b.b.create_blend_state = si_create_blend_state;
 	sctx->b.b.bind_blend_state = si_bind_blend_state;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 563d9ab9ae3..a69d5962503 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -149,36 +149,6 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 		S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
 }
 
-#define SIX_BITS 0x3F
-
-static void si_emit_clip_state(struct si_context *sctx)
-{
-	struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
-	struct tgsi_shader_info *info = si_get_vs_info(sctx);
-	struct si_shader *vs = si_get_vs_state(sctx);
-	unsigned window_space =
-	   vs->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
-	unsigned clipdist_mask =
-		info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
-
-	r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
-		S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
-		S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
-		S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
-		S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
-		S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
-		S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
-					    info->writes_edgeflag ||
-					    info->writes_layer) |
-		(sctx->queued.named.rasterizer->clip_plane_enable &
-		 clipdist_mask));
-	r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
-		sctx->queued.named.rasterizer->pa_cl_clip_cntl |
-		(clipdist_mask ? 0 :
-		 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
-		S_028810_CLIP_DISABLE(window_space));
-}
-
 static void si_emit_rasterizer_prim_state(struct si_context *sctx, unsigned mode)
 {
 	struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
@@ -548,7 +518,6 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 	}
 
 	si_pm4_emit_dirty(sctx);
-	si_emit_clip_state(sctx);
 	si_emit_rasterizer_prim_state(sctx, info->mode);
 	si_emit_draw_registers(sctx, info, &ib);
 	si_emit_draw_packets(sctx, info, &ib);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 22a736c1e88..f2717b073aa 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -499,6 +499,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
 		return;
 
 	sctx->vs_shader = sel;
+	sctx->clip_regs.dirty = true;
 }
 
 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
@@ -510,6 +511,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
 		return;
 
 	sctx->gs_shader = sel;
+	sctx->clip_regs.dirty = true;
 }
 
 static void si_make_dummy_ps(struct si_context *sctx)