diff options
| author | Jordan Justen <[email protected]> | 2016-04-17 13:48:28 -0700 |
|---|---|---|
| committer | Jordan Justen <[email protected]> | 2016-05-04 11:23:17 -0700 |
| commit | ac0bbf9ef39b14e53045431ef7817a5b37807328 (patch) | |
| tree | ef7f6807637d342b27b7e06104c7b089d1007fbe | |
| parent | 9f581f8f2407472be262bea8c82acde6ce29f2fb (diff) | |
i965: Add MI_MATH reg defs for HSW+
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_reg.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index 365c045b8b0..01b435864e3 100644 --- a/src/mesa/drivers/dri/i965/intel_reg.h +++ b/src/mesa/drivers/dri/i965/intel_reg.h @@ -63,6 +63,42 @@ # define MI_PREDICATE_COMPAREOP_SRCS_EQUAL (2 << 0) # define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL (3 << 0) +#define HSW_MI_MATH (CMD_MI | (0x1a << 23)) + +#define MI_MATH_ALU2(opcode, operand1, operand2) \ + ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) | \ + ((MI_MATH_OPERAND_##operand2) << 0) ) + +#define MI_MATH_ALU1(opcode, operand1) \ + ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) ) + +#define MI_MATH_ALU0(opcode) \ + ( ((MI_MATH_OPCODE_##opcode) << 20) ) + +#define MI_MATH_OPCODE_NOOP 0x000 +#define MI_MATH_OPCODE_LOAD 0x080 +#define MI_MATH_OPCODE_LOADINV 0x480 +#define MI_MATH_OPCODE_LOAD0 0x081 +#define MI_MATH_OPCODE_LOAD1 0x481 +#define MI_MATH_OPCODE_ADD 0x100 +#define MI_MATH_OPCODE_SUB 0x101 +#define MI_MATH_OPCODE_AND 0x102 +#define MI_MATH_OPCODE_OR 0x103 +#define MI_MATH_OPCODE_XOR 0x104 +#define MI_MATH_OPCODE_STORE 0x180 +#define MI_MATH_OPCODE_STOREINV 0x580 + +#define MI_MATH_OPERAND_R0 0x00 +#define MI_MATH_OPERAND_R1 0x01 +#define MI_MATH_OPERAND_R2 0x02 +#define MI_MATH_OPERAND_R3 0x03 +#define MI_MATH_OPERAND_R4 0x04 +#define MI_MATH_OPERAND_SRCA 0x20 +#define MI_MATH_OPERAND_SRCB 0x21 +#define MI_MATH_OPERAND_ACCU 0x31 +#define MI_MATH_OPERAND_ZF 0x32 +#define MI_MATH_OPERAND_CF 0x33 + /** @{ * * PIPE_CONTROL operation, a combination MI_FLUSH and register write with @@ -193,6 +229,8 @@ #define MI_PREDICATE_RESULT_1 0x241C #define MI_PREDICATE_RESULT_2 0x2214 +#define HSW_CS_GPR(n) (0x2600 + (n) * 8) + /* L3 cache control registers. */ #define GEN7_L3SQCREG1 0xb010 /* L3SQ general and high priority credit initialization. */ |