diff options
| author | Ilia Mirkin <[email protected]> | 2016-03-09 01:04:58 -0500 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2016-03-10 22:34:28 -0500 |
| commit | a8819fb1fff4fa64ff6aef9435682fe7633cd2a4 (patch) | |
| tree | 5c2290fae7abfee7d1bdf648ab3b9143ef6e10c9 | |
| parent | 59c5508b9ab357c47aa07dfec6d74fec9d0843aa (diff) | |
nvc0: add support for TGSI FMA ops
This will allow the nouveau backend to not try and split up ops that are
fused in GLSL.
Signed-off-by: Ilia Mirkin <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index 868372202f9..b06d86ad760 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -525,6 +525,7 @@ nv50_ir::DataType Instruction::inferSrcType() const case TGSI_OPCODE_DRCP: case TGSI_OPCODE_DSQRT: case TGSI_OPCODE_DMAD: + case TGSI_OPCODE_DFMA: case TGSI_OPCODE_DFRAC: case TGSI_OPCODE_DRSQ: case TGSI_OPCODE_DTRUNC: @@ -624,6 +625,7 @@ static nv50_ir::operation translateOpcode(uint opcode) NV50_IR_OPCODE_CASE(SLT, SET); NV50_IR_OPCODE_CASE(SGE, SET); NV50_IR_OPCODE_CASE(MAD, MAD); + NV50_IR_OPCODE_CASE(FMA, FMA); NV50_IR_OPCODE_CASE(SUB, SUB); NV50_IR_OPCODE_CASE(FLR, FLOOR); @@ -723,6 +725,7 @@ static nv50_ir::operation translateOpcode(uint opcode) NV50_IR_OPCODE_CASE(DRCP, RCP); NV50_IR_OPCODE_CASE(DSQRT, SQRT); NV50_IR_OPCODE_CASE(DMAD, MAD); + NV50_IR_OPCODE_CASE(DFMA, FMA); NV50_IR_OPCODE_CASE(D2I, CVT); NV50_IR_OPCODE_CASE(D2U, CVT); NV50_IR_OPCODE_CASE(I2D, CVT); @@ -2672,6 +2675,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) case TGSI_OPCODE_MAD: case TGSI_OPCODE_UMAD: case TGSI_OPCODE_SAD: + case TGSI_OPCODE_FMA: FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) { src0 = fetchSrc(0, c); src1 = fetchSrc(1, c); @@ -3395,6 +3399,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) } break; case TGSI_OPCODE_DMAD: + case TGSI_OPCODE_DFMA: FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) { src0 = getSSA(8); src1 = getSSA(8); diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 114d868e919..30afdf2f03c 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -337,8 +337,9 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 1; case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: return 1; - case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: + return 1; + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 0; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: |