diff options
| author | Nicolai Hähnle <[email protected]> | 2018-06-28 20:53:51 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-03 15:51:12 -0400 |
| commit | a66be784c32ea08e0eae00fe4de9b2e1b42cb53d (patch) | |
| tree | 48ebc7b73441f0a99b6f961c46f3ca38beef21df | |
| parent | 97ddcfff7c50347b13701a156f9ac4942e0caaf7 (diff) | |
ac/surface/gfx10: DCC is only supported with SW_64KB_{Z,R}_X modes
Acked-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/amd/common/ac_surface.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 298dfe20838..8168b2e97bc 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1004,6 +1004,14 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, return 0; } +static bool gfx9_is_dcc_capable(const struct radeon_info *info, unsigned sw_mode) +{ + if (info->chip_class >= GFX10) + return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X; + + return sw_mode != ADDR_SW_LINEAR; +} + static int gfx9_compute_miptree(ADDR_HANDLE addrlib, const struct radeon_info *info, const struct ac_surf_config *config, @@ -1114,9 +1122,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, } /* DCC */ - if (!(surf->flags & RADEON_SURF_DISABLE_DCC) && - !compressed && - in->swizzleMode != ADDR_SW_LINEAR) { + if (!(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && + gfx9_is_dcc_capable(info, in->swizzleMode)) { ADDR2_COMPUTE_DCCINFO_INPUT din = {0}; ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0}; ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {}; |