i965: Convert brw_eu_emit.c to the new brw_inst API.

v2:
 - Fix IF -> ELSE patching on Sandybridge.
 - Don't set base_mrf on Gen6+ in OWord Block Read functions.  (Although
 - the old code did this universally, it shouldn't have - the field
 - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.)

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>

1 files changed, 461 insertions, 482 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index ab61868bb75..45eab294a08 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -44,10 +44,14 @@ static void guess_execution_size(struct brw_compile *p,
 				 struct brw_instruction *insn,
 				 struct brw_reg reg)
 {
-   if (reg.width == BRW_WIDTH_8 && p->compressed)
-      insn->header.execution_size = BRW_EXECUTE_16;
-   else
-      insn->header.execution_size = reg.width;	/* note - definitions are compatible */
+   const struct brw_context *brw = p->brw;
+
+   if (reg.width == BRW_WIDTH_8 && p->compressed) {
+      brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_16);
+   } else {
+      /* Register width definitions are compatible with BRW_EXECUTE_* enums. */
+      brw_inst_set_exec_size(brw, insn, reg.width);
+   }
 }
 
 
@@ -156,31 +160,33 @@ brw_reg_type_to_hw_type(const struct brw_context *brw,
 }
 
 void
-brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
+brw_set_dest(struct brw_compile *p, struct brw_instruction *inst,
 	     struct brw_reg dest)
 {
+   const struct brw_context *brw = p->brw;
+
    if (dest.file != BRW_ARCHITECTURE_REGISTER_FILE &&
        dest.file != BRW_MESSAGE_REGISTER_FILE)
       assert(dest.nr < 128);
 
    gen7_convert_mrf_to_grf(p, &dest);
 
-   insn->bits1.da1.dest_reg_file = dest.file;
-   insn->bits1.da1.dest_reg_type =
-      brw_reg_type_to_hw_type(p->brw, dest.type, dest.file);
-   insn->bits1.da1.dest_address_mode = dest.address_mode;
+   brw_inst_set_dst_reg_file(brw, inst, dest.file);
+   brw_inst_set_dst_reg_type(brw, inst, brw_reg_type_to_hw_type(brw, dest.type,
+                                                                dest.file));
+   brw_inst_set_dst_address_mode(brw, inst, dest.address_mode);
 
    if (dest.address_mode == BRW_ADDRESS_DIRECT) {
-      insn->bits1.da1.dest_reg_nr = dest.nr;
+      brw_inst_set_dst_da_reg_nr(brw, inst, dest.nr);
 
-      if (insn->header.access_mode == BRW_ALIGN_1) {
-	 insn->bits1.da1.dest_subreg_nr = dest.subnr;
+      if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
+         brw_inst_set_dst_da1_subreg_nr(brw, inst, dest.subnr);
 	 if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
 	    dest.hstride = BRW_HORIZONTAL_STRIDE_1;
-	 insn->bits1.da1.dest_horiz_stride = dest.hstride;
+         brw_inst_set_dst_hstride(brw, inst, dest.hstride);
       } else {
-	 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
-	 insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
+         brw_inst_set_dst_da16_subreg_nr(brw, inst, dest.subnr / 16);
+         brw_inst_set_da16_writemask(brw, inst, dest.dw1.bits.writemask);
          if (dest.file == BRW_GENERAL_REGISTER_FILE ||
              dest.file == BRW_MESSAGE_REGISTER_FILE) {
             assert(dest.dw1.bits.writemask != 0);
@@ -189,35 +195,38 @@ brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
 	  *    Although Dst.HorzStride is a don't care for Align16, HW needs
 	  *    this to be programmed as "01".
 	  */
-	 insn->bits1.da16.dest_horiz_stride = 1;
+         brw_inst_set_dst_hstride(brw, inst, 1);
       }
    } else {
-      insn->bits1.ia1.dest_subreg_nr = dest.subnr;
+      brw_inst_set_dst_ia_subreg_nr(brw, inst, dest.subnr);
 
       /* These are different sizes in align1 vs align16:
        */
-      if (insn->header.access_mode == BRW_ALIGN_1) {
-	 insn->bits1.ia1.dest_indirect_offset = dest.dw1.bits.indirect_offset;
+      if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
+         brw_inst_set_dst_ia1_addr_imm(brw, inst,
+                                       dest.dw1.bits.indirect_offset);
 	 if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
 	    dest.hstride = BRW_HORIZONTAL_STRIDE_1;
-	 insn->bits1.ia1.dest_horiz_stride = dest.hstride;
+         brw_inst_set_dst_hstride(brw, inst, dest.hstride);
       } else {
-	 insn->bits1.ia16.dest_indirect_offset = dest.dw1.bits.indirect_offset;
+         brw_inst_set_dst_ia16_addr_imm(brw, inst,
+                                        dest.dw1.bits.indirect_offset);
 	 /* even ignored in da16, still need to set as '01' */
-	 insn->bits1.ia16.dest_horiz_stride = 1;
+         brw_inst_set_dst_hstride(brw, inst, 1);
       }
    }
 
    /* NEW: Set the execution size based on dest.width and
-    * insn->compression_control:
+    * inst->compression_control:
     */
-   guess_execution_size(p, insn, dest);
+   guess_execution_size(p, inst, dest);
 }
 
 extern int reg_type_size[];
 
 static void
-validate_reg(struct brw_instruction *insn, struct brw_reg reg)
+validate_reg(const struct brw_context *brw,
+             struct brw_instruction *inst, struct brw_reg reg)
 {
    int hstride_for_reg[] = {0, 1, 2, 4};
    int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
@@ -231,8 +240,8 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
        * destination horiz stride has to be a word.
        */
       if (reg.type == BRW_REGISTER_TYPE_V) {
-	 assert(hstride_for_reg[insn->bits1.da1.dest_horiz_stride] *
-		reg_type_size[insn->bits1.da1.dest_reg_type] == 2);
+         assert(hstride_for_reg[brw_inst_dst_hstride(brw, inst)] *
+                reg_type_size[brw_inst_dst_reg_type(brw, inst)] == 2);
       }
 
       return;
@@ -255,9 +264,9 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg)
    assert(reg.width >= 0 && reg.width < Elements(width_for_reg));
    width = width_for_reg[reg.width];
 
-   assert(insn->header.execution_size >= 0 &&
-	  insn->header.execution_size < Elements(execsize_for_reg));
-   execsize = execsize_for_reg[insn->header.execution_size];
+   assert(brw_inst_exec_size(brw, inst) >= 0 &&
+          brw_inst_exec_size(brw, inst) < Elements(execsize_for_reg));
+   execsize = execsize_for_reg[brw_inst_exec_size(brw, inst)];
 
    /* Restrictions from 3.3.10: Register Region Restrictions. */
    /* 3. */
@@ -303,7 +312,7 @@ is_compactable_immediate(unsigned imm)
 }
 
 void
-brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
+brw_set_src0(struct brw_compile *p, struct brw_instruction *inst,
 	     struct brw_reg reg)
 {
    struct brw_context *brw = p->brw;
@@ -313,8 +322,8 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
 
    gen7_convert_mrf_to_grf(p, &reg);
 
-   if (brw->gen >= 6 && (insn->header.opcode == BRW_OPCODE_SEND ||
-                           insn->header.opcode == BRW_OPCODE_SENDC)) {
+   if (brw->gen >= 6 && (brw_inst_opcode(brw, inst) == BRW_OPCODE_SEND ||
+                         brw_inst_opcode(brw, inst) == BRW_OPCODE_SENDC)) {
       /* Any source modifiers or regions will be ignored, since this just
        * identifies the MRF/GRF to start reading the message contents from.
        * Check for some likely failures.
@@ -324,17 +333,17 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
       assert(reg.address_mode == BRW_ADDRESS_DIRECT);
    }
 
-   validate_reg(insn, reg);
+   validate_reg(brw, inst, reg);
 
-   insn->bits1.da1.src0_reg_file = reg.file;
-   insn->bits1.da1.src0_reg_type =
-      brw_reg_type_to_hw_type(brw, reg.type, reg.file);
-   insn->bits2.da1.src0_abs = reg.abs;
-   insn->bits2.da1.src0_negate = reg.negate;
-   insn->bits2.da1.src0_address_mode = reg.address_mode;
+   brw_inst_set_src0_reg_file(brw, inst, reg.file);
+   brw_inst_set_src0_reg_type(brw, inst,
+                              brw_reg_type_to_hw_type(brw, reg.type, reg.file));
+   brw_inst_set_src0_abs(brw, inst, reg.abs);
+   brw_inst_set_src0_negate(brw, inst, reg.negate);
+   brw_inst_set_src0_address_mode(brw, inst, reg.address_mode);
 
    if (reg.file == BRW_IMMEDIATE_VALUE) {
-      insn->bits3.ud = reg.dw1.ud;
+      brw_inst_set_imm_ud(brw, inst, reg.dw1.ud);
 
       /* The Bspec's section titled "Non-present Operands" claims that if src0
        * is an immediate that src1's type must be the same as that of src0.
@@ -358,11 +367,12 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
        * so it's not clear whether it has the restriction. We'll assume it was
        * lifted on SNB. (FINISHME: decode the GM45 tables and check.)
        */
-      insn->bits1.da1.src1_reg_file = 0; /* arf */
+      brw_inst_set_src1_reg_file(brw, inst, BRW_ARCHITECTURE_REGISTER_FILE);
       if (brw->gen < 6) {
-         insn->bits1.da1.src1_reg_type = insn->bits1.da1.src0_reg_type;
+         brw_inst_set_src1_reg_type(brw, inst,
+                                    brw_inst_src0_reg_type(brw, inst));
       } else {
-         insn->bits1.da1.src1_reg_type = BRW_HW_REG_TYPE_UD;
+         brw_inst_set_src1_reg_type(brw, inst, BRW_HW_REG_TYPE_UD);
       }
 
       /* Compacted instructions only have 12-bits (plus 1 for the other 20)
@@ -376,64 +386,67 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
        *
        * If we see a 0.0:F, change the type to VF so that it can be compacted.
        */
-      if (insn->bits3.ud == 0x0 &&
-          insn->bits1.da1.src0_reg_type == BRW_HW_REG_TYPE_F) {
-         insn->bits1.da1.src0_reg_type = BRW_HW_REG_IMM_TYPE_VF;
+      if (brw_inst_imm_ud(brw, inst) == 0x0 &&
+          brw_inst_src0_reg_type(brw, inst) == BRW_HW_REG_TYPE_F) {
+         brw_inst_set_src0_reg_type(brw, inst, BRW_HW_REG_IMM_TYPE_VF);
       }
 
       /* There are no mappings for dst:d | i:d, so if the immediate is suitable
        * set the types to :UD so the instruction can be compacted.
        */
-      if (is_compactable_immediate(insn->bits3.ud) &&
-          insn->header.destreg__conditionalmod == BRW_CONDITIONAL_NONE &&
-          insn->bits1.da1.src0_reg_type == BRW_HW_REG_TYPE_D &&
-          insn->bits1.da1.dest_reg_type == BRW_HW_REG_TYPE_D) {
-         insn->bits1.da1.src0_reg_type = BRW_HW_REG_TYPE_UD;
-         insn->bits1.da1.dest_reg_type = BRW_HW_REG_TYPE_UD;
+      if (is_compactable_immediate(brw_inst_imm_ud(brw, inst)) &&
+          brw_inst_cond_modifier(brw, inst) == BRW_CONDITIONAL_NONE &&
+          brw_inst_src0_reg_type(brw, inst) == BRW_HW_REG_TYPE_D &&
+          brw_inst_dst_reg_type(brw, inst) == BRW_HW_REG_TYPE_D) {
+         brw_inst_set_src0_reg_type(brw, inst, BRW_HW_REG_TYPE_UD);
+         brw_inst_set_dst_reg_type(brw, inst, BRW_HW_REG_TYPE_UD);
       }
    } else {
       if (reg.address_mode == BRW_ADDRESS_DIRECT) {
-	 if (insn->header.access_mode == BRW_ALIGN_1) {
-	    insn->bits2.da1.src0_subreg_nr = reg.subnr;
-	    insn->bits2.da1.src0_reg_nr = reg.nr;
+         brw_inst_set_src0_da_reg_nr(brw, inst, reg.nr);
+         if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
+             brw_inst_set_src0_da1_subreg_nr(brw, inst, reg.subnr);
 	 } else {
-	    insn->bits2.da16.src0_subreg_nr = reg.subnr / 16;
-	    insn->bits2.da16.src0_reg_nr = reg.nr;
+            brw_inst_set_src0_da16_subreg_nr(brw, inst, reg.subnr / 16);
 	 }
       } else {
-	 insn->bits2.ia1.src0_subreg_nr = reg.subnr;
+         brw_inst_set_src0_ia_subreg_nr(brw, inst, reg.subnr);
 
-	 if (insn->header.access_mode == BRW_ALIGN_1) {
-	    insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
+         if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
+            brw_inst_set_src0_ia1_addr_imm(brw, inst, reg.dw1.bits.indirect_offset);
 	 } else {
-	    insn->bits2.ia16.src0_subreg_nr = reg.dw1.bits.indirect_offset;
+            brw_inst_set_src0_ia_subreg_nr(brw, inst, reg.dw1.bits.indirect_offset);
 	 }
       }
 
-      if (insn->header.access_mode == BRW_ALIGN_1) {
+      if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
 	 if (reg.width == BRW_WIDTH_1 &&
-	     insn->header.execution_size == BRW_EXECUTE_1) {
-	    insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
-	    insn->bits2.da1.src0_width = BRW_WIDTH_1;
-	    insn->bits2.da1.src0_vert_stride = BRW_VERTICAL_STRIDE_0;
+             brw_inst_exec_size(brw, inst) == BRW_EXECUTE_1) {
+            brw_inst_set_src0_hstride(brw, inst, BRW_HORIZONTAL_STRIDE_0);
+            brw_inst_set_src0_width(brw, inst, BRW_WIDTH_1);
+            brw_inst_set_src0_vstride(brw, inst, BRW_VERTICAL_STRIDE_0);
 	 } else {
-	    insn->bits2.da1.src0_horiz_stride = reg.hstride;
-	    insn->bits2.da1.src0_width = reg.width;
-	    insn->bits2.da1.src0_vert_stride = reg.vstride;
+            brw_inst_set_src0_hstride(brw, inst, reg.hstride);
+            brw_inst_set_src0_width(brw, inst, reg.width);
+            brw_inst_set_src0_vstride(brw, inst, reg.vstride);
 	 }
       } else {
-	 insn->bits2.da16.src0_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
-	 insn->bits2.da16.src0_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y);
-	 insn->bits2.da16.src0_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z);
-	 insn->bits2.da16.src0_swz_w = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W);
+         brw_inst_set_src0_da16_swiz_x(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X));
+         brw_inst_set_src0_da16_swiz_y(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y));
+         brw_inst_set_src0_da16_swiz_z(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z));
+         brw_inst_set_src0_da16_swiz_w(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W));
 
 	 /* This is an oddity of the fact we're using the same
 	  * descriptions for registers in align_16 as align_1:
 	  */
 	 if (reg.vstride == BRW_VERTICAL_STRIDE_8)
-	    insn->bits2.da16.src0_vert_stride = BRW_VERTICAL_STRIDE_4;
+            brw_inst_set_src0_vstride(brw, inst, BRW_VERTICAL_STRIDE_4);
 	 else
-	    insn->bits2.da16.src0_vert_stride = reg.vstride;
+            brw_inst_set_src0_vstride(brw, inst, reg.vstride);
       }
    }
 }
@@ -441,9 +454,10 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
 
 void
 brw_set_src1(struct brw_compile *p,
-             struct brw_instruction *insn,
+             struct brw_instruction *inst,
              struct brw_reg reg)
 {
+   const struct brw_context *brw = p->brw;
    assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
 
    if (reg.type != BRW_ARCHITECTURE_REGISTER_FILE)
@@ -451,20 +465,20 @@ brw_set_src1(struct brw_compile *p,
 
    gen7_convert_mrf_to_grf(p, &reg);
 
-   validate_reg(insn, reg);
+   validate_reg(brw, inst, reg);
 
-   insn->bits1.da1.src1_reg_file = reg.file;
-   insn->bits1.da1.src1_reg_type =
-      brw_reg_type_to_hw_type(p->brw, reg.type, reg.file);
-   insn->bits3.da1.src1_abs = reg.abs;
-   insn->bits3.da1.src1_negate = reg.negate;
+   brw_inst_set_src1_reg_file(brw, inst, reg.file);
+   brw_inst_set_src1_reg_type(brw, inst,
+                              brw_reg_type_to_hw_type(brw, reg.type, reg.file));
+   brw_inst_set_src1_abs(brw, inst, reg.abs);
+   brw_inst_set_src1_negate(brw, inst, reg.negate);
 
    /* Only src1 can be immediate in two-argument instructions.
     */
-   assert(insn->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE);
+   assert(brw_inst_src0_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE);
 
    if (reg.file == BRW_IMMEDIATE_VALUE) {
-      insn->bits3.ud = reg.dw1.ud;
+      brw_inst_set_imm_ud(brw, inst, reg.dw1.ud);
    } else {
       /* This is a hardware restriction, which may or may not be lifted
        * in the future:
@@ -472,38 +486,41 @@ brw_set_src1(struct brw_compile *p,
       assert (reg.address_mode == BRW_ADDRESS_DIRECT);
       /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
 
-      if (insn->header.access_mode == BRW_ALIGN_1) {
-	 insn->bits3.da1.src1_subreg_nr = reg.subnr;
-	 insn->bits3.da1.src1_reg_nr = reg.nr;
+      brw_inst_set_src1_da_reg_nr(brw, inst, reg.nr);
+      if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
+         brw_inst_set_src1_da1_subreg_nr(brw, inst, reg.subnr);
       } else {
-	 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16;
-	 insn->bits3.da16.src1_reg_nr = reg.nr;
+         brw_inst_set_src1_da16_subreg_nr(brw, inst, reg.subnr / 16);
       }
 
-      if (insn->header.access_mode == BRW_ALIGN_1) {
+      if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
 	 if (reg.width == BRW_WIDTH_1 &&
-	     insn->header.execution_size == BRW_EXECUTE_1) {
-	    insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
-	    insn->bits3.da1.src1_width = BRW_WIDTH_1;
-	    insn->bits3.da1.src1_vert_stride = BRW_VERTICAL_STRIDE_0;
+             brw_inst_exec_size(brw, inst) == BRW_EXECUTE_1) {
+            brw_inst_set_src1_hstride(brw, inst, BRW_HORIZONTAL_STRIDE_0);
+            brw_inst_set_src1_width(brw, inst, BRW_WIDTH_1);
+            brw_inst_set_src1_vstride(brw, inst, BRW_VERTICAL_STRIDE_0);
 	 } else {
-	    insn->bits3.da1.src1_horiz_stride = reg.hstride;
-	    insn->bits3.da1.src1_width = reg.width;
-	    insn->bits3.da1.src1_vert_stride = reg.vstride;
+            brw_inst_set_src1_hstride(brw, inst, reg.hstride);
+            brw_inst_set_src1_width(brw, inst, reg.width);
+            brw_inst_set_src1_vstride(brw, inst, reg.vstride);
 	 }
       } else {
-	 insn->bits3.da16.src1_swz_x = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X);
-	 insn->bits3.da16.src1_swz_y = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y);
-	 insn->bits3.da16.src1_swz_z = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z);
-	 insn->bits3.da16.src1_swz_w = BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W);
+         brw_inst_set_src1_da16_swiz_x(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X));
+         brw_inst_set_src1_da16_swiz_y(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y));
+         brw_inst_set_src1_da16_swiz_z(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z));
+         brw_inst_set_src1_da16_swiz_w(brw, inst,
+            BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W));
 
 	 /* This is an oddity of the fact we're using the same
 	  * descriptions for registers in align_16 as align_1:
 	  */
 	 if (reg.vstride == BRW_VERTICAL_STRIDE_8)
-	    insn->bits3.da16.src1_vert_stride = BRW_VERTICAL_STRIDE_4;
+            brw_inst_set_src1_vstride(brw, inst, BRW_VERTICAL_STRIDE_4);
 	 else
-	    insn->bits3.da16.src1_vert_stride = reg.vstride;
+            brw_inst_set_src1_vstride(brw, inst, reg.vstride);
       }
    }
 }
@@ -528,31 +545,18 @@ brw_set_message_descriptor(struct brw_compile *p,
    struct brw_context *brw = p->brw;
 
    brw_set_src1(p, inst, brw_imm_d(0));
+   brw_inst_set_sfid(brw, inst, sfid);
+   brw_inst_set_mlen(brw, inst, msg_length);
+   brw_inst_set_rlen(brw, inst, response_length);
+   brw_inst_set_eot(brw, inst, end_of_thread);
 
    if (brw->gen >= 5) {
-      inst->bits3.generic_gen5.header_present = header_present;
-      inst->bits3.generic_gen5.response_length = response_length;
-      inst->bits3.generic_gen5.msg_length = msg_length;
-      inst->bits3.generic_gen5.end_of_thread = end_of_thread;
-
-      if (brw->gen >= 6) {
-	 /* On Gen6+ Message target/SFID goes in bits 27:24 of the header */
-	 inst->header.destreg__conditionalmod = sfid;
-      } else {
-	 /* Set Extended Message Descriptor (ex_desc) */
-	 inst->bits2.send_gen5.sfid = sfid;
-	 inst->bits2.send_gen5.end_of_thread = end_of_thread;
-      }
-   } else {
-      inst->bits3.generic.response_length = response_length;
-      inst->bits3.generic.msg_length = msg_length;
-      inst->bits3.generic.msg_target = sfid;
-      inst->bits3.generic.end_of_thread = end_of_thread;
+      brw_inst_set_header_present(brw, inst, header_present);
    }
 }
 
 static void brw_set_math_message( struct brw_compile *p,
-				  struct brw_instruction *insn,
+				  struct brw_instruction *inst,
 				  unsigned function,
 				  unsigned integer_type,
 				  bool low_precision,
@@ -587,23 +591,14 @@ static void brw_set_math_message( struct brw_compile *p,
    }
 
 
-   brw_set_message_descriptor(p, insn, BRW_SFID_MATH,
+   brw_set_message_descriptor(p, inst, BRW_SFID_MATH,
 			      msg_length, response_length, false, false);
-   if (brw->gen == 5) {
-      insn->bits3.math_gen5.function = function;
-      insn->bits3.math_gen5.int_type = integer_type;
-      insn->bits3.math_gen5.precision = low_precision;
-      insn->bits3.math_gen5.saturate = insn->header.saturate;
-      insn->bits3.math_gen5.data_type = dataType;
-      insn->bits3.math_gen5.snapshot = 0;
-   } else {
-      insn->bits3.math.function = function;
-      insn->bits3.math.int_type = integer_type;
-      insn->bits3.math.precision = low_precision;
-      insn->bits3.math.saturate = insn->header.saturate;
-      insn->bits3.math.data_type = dataType;
-   }
-   insn->header.saturate = 0;
+   brw_inst_set_math_msg_function(brw, inst, function);
+   brw_inst_set_math_msg_signed_int(brw, inst, integer_type);
+   brw_inst_set_math_msg_precision(brw, inst, low_precision);
+   brw_inst_set_math_msg_saturate(brw, inst, brw_inst_saturate(brw, inst));
+   brw_inst_set_math_msg_data_type(brw, inst, dataType);
+   brw_inst_set_saturate(brw, inst, 0);
 }
 
 
@@ -613,14 +608,17 @@ static void brw_set_ff_sync_message(struct brw_compile *p,
 				    unsigned response_length,
 				    bool end_of_thread)
 {
+   const struct brw_context *brw = p->brw;
+
    brw_set_message_descriptor(p, insn, BRW_SFID_URB,
 			      1, response_length, true, end_of_thread);
-   insn->bits3.urb_gen5.opcode = 1; /* FF_SYNC */
-   insn->bits3.urb_gen5.offset = 0; /* Not used by FF_SYNC */
-   insn->bits3.urb_gen5.swizzle_control = 0; /* Not used by FF_SYNC */
-   insn->bits3.urb_gen5.allocate = allocate;
-   insn->bits3.urb_gen5.used = 0; /* Not used by FF_SYNC */
-   insn->bits3.urb_gen5.complete = 0; /* Not used by FF_SYNC */
+   brw_inst_set_urb_opcode(brw, insn, 1); /* FF_SYNC */
+   brw_inst_set_urb_allocate(brw, insn, allocate);
+   /* The following fields are not used by FF_SYNC: */
+   brw_inst_set_urb_global_offset(brw, insn, 0);
+   brw_inst_set_urb_swizzle_control(brw, insn, 0);
+   brw_inst_set_urb_used(brw, insn, 0);
+   brw_inst_set_urb_complete(brw, insn, 0);
 }
 
 static void brw_set_urb_message( struct brw_compile *p,
@@ -633,36 +631,34 @@ static void brw_set_urb_message( struct brw_compile *p,
 {
    struct brw_context *brw = p->brw;
 
+   assert(brw->gen < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
+   assert(brw->gen < 7 || !(flags & BRW_URB_WRITE_ALLOCATE));
+   assert(brw->gen >= 7 || !(flags & BRW_URB_WRITE_PER_SLOT_OFFSET));
+
    brw_set_message_descriptor(p, insn, BRW_SFID_URB,
 			      msg_length, response_length, true,
                               flags & BRW_URB_WRITE_EOT);
-   if (brw->gen == 7) {
-      if (flags & BRW_URB_WRITE_OWORD) {
-         assert(msg_length == 2); /* header + one OWORD of data */
-         insn->bits3.urb_gen7.opcode = BRW_URB_OPCODE_WRITE_OWORD;
-      } else {
-         insn->bits3.urb_gen7.opcode = BRW_URB_OPCODE_WRITE_HWORD;
-      }
-      insn->bits3.urb_gen7.offset = offset;
-      assert(swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
-      insn->bits3.urb_gen7.swizzle_control = swizzle_control;
-      insn->bits3.urb_gen7.per_slot_offset =
-         flags & BRW_URB_WRITE_PER_SLOT_OFFSET ? 1 : 0;
-      insn->bits3.urb_gen7.complete = flags & BRW_URB_WRITE_COMPLETE ? 1 : 0;
-   } else if (brw->gen >= 5) {
-      insn->bits3.urb_gen5.opcode = 0;	/* URB_WRITE */
-      insn->bits3.urb_gen5.offset = offset;
-      insn->bits3.urb_gen5.swizzle_control = swizzle_control;
-      insn->bits3.urb_gen5.allocate = flags & BRW_URB_WRITE_ALLOCATE ? 1 : 0;
-      insn->bits3.urb_gen5.used = flags & BRW_URB_WRITE_UNUSED ? 0 : 1;
-      insn->bits3.urb_gen5.complete = flags & BRW_URB_WRITE_COMPLETE ? 1 : 0;
+
+   if (flags & BRW_URB_WRITE_OWORD) {
+      assert(msg_length == 2); /* header + one OWORD of data */
+      brw_inst_set_urb_opcode(brw, insn, BRW_URB_OPCODE_WRITE_OWORD);
+   } else {
+      brw_inst_set_urb_opcode(brw, insn, BRW_URB_OPCODE_WRITE_HWORD);
+   }
+
+   brw_inst_set_urb_global_offset(brw, insn, offset);
+   brw_inst_set_urb_swizzle_control(brw, insn, swizzle_control);
+
+   if (brw->gen < 8) {
+      brw_inst_set_urb_complete(brw, insn, !!(flags & BRW_URB_WRITE_COMPLETE));
+   }
+
+   if (brw->gen < 7) {
+      brw_inst_set_urb_allocate(brw, insn, !!(flags & BRW_URB_WRITE_ALLOCATE));
+      brw_inst_set_urb_used(brw, insn, !(flags & BRW_URB_WRITE_UNUSED));
    } else {
-      insn->bits3.urb.opcode = 0;	/* ? */
-      insn->bits3.urb.offset = offset;
-      insn->bits3.urb.swizzle_control = swizzle_control;
-      insn->bits3.urb.allocate = flags & BRW_URB_WRITE_ALLOCATE ? 1 : 0;
-      insn->bits3.urb.used = flags & BRW_URB_WRITE_UNUSED ? 0 : 1;
-      insn->bits3.urb.complete = flags & BRW_URB_WRITE_COMPLETE ? 1 : 0;
+      brw_inst_set_urb_per_slot_offset(brw, insn,
+         !!(flags & BRW_URB_WRITE_PER_SLOT_OFFSET));
    }
 }
 
@@ -698,29 +694,12 @@ brw_set_dp_write_message(struct brw_compile *p,
    brw_set_message_descriptor(p, insn, sfid, msg_length, response_length,
 			      header_present, end_of_thread);
 
-   if (brw->gen >= 7) {
-      insn->bits3.gen7_dp.binding_table_index = binding_table_index;
-      insn->bits3.gen7_dp.msg_control = msg_control;
-      insn->bits3.gen7_dp.last_render_target = last_render_target;
-      insn->bits3.gen7_dp.msg_type = msg_type;
-   } else if (brw->gen == 6) {
-      insn->bits3.gen6_dp.binding_table_index = binding_table_index;
-      insn->bits3.gen6_dp.msg_control = msg_control;
-      insn->bits3.gen6_dp.last_render_target = last_render_target;
-      insn->bits3.gen6_dp.msg_type = msg_type;
-      insn->bits3.gen6_dp.send_commit_msg = send_commit_msg;
-   } else if (brw->gen == 5) {
-      insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
-      insn->bits3.dp_write_gen5.msg_control = msg_control;
-      insn->bits3.dp_write_gen5.last_render_target = last_render_target;
-      insn->bits3.dp_write_gen5.msg_type = msg_type;
-      insn->bits3.dp_write_gen5.send_commit_msg = send_commit_msg;
-   } else {
-      insn->bits3.dp_write.binding_table_index = binding_table_index;
-      insn->bits3.dp_write.msg_control = msg_control;
-      insn->bits3.dp_write.last_render_target = last_render_target;
-      insn->bits3.dp_write.msg_type = msg_type;
-      insn->bits3.dp_write.send_commit_msg = send_commit_msg;
+   brw_inst_set_binding_table_index(brw, insn, binding_table_index);
+   brw_inst_set_dp_write_msg_type(brw, insn, msg_type);
+   brw_inst_set_dp_write_msg_control(brw, insn, msg_control);
+   brw_inst_set_rt_last(brw, insn, last_render_target);
+   if (brw->gen < 7) {
+      brw_inst_set_dp_write_commit(brw, insn, send_commit_msg);
    }
 }
 
@@ -752,38 +731,16 @@ brw_set_dp_read_message(struct brw_compile *p,
    brw_set_message_descriptor(p, insn, sfid, msg_length, response_length,
 			      header_present, false);
 
-   if (brw->gen >= 7) {
-      insn->bits3.gen7_dp.binding_table_index = binding_table_index;
-      insn->bits3.gen7_dp.msg_control = msg_control;
-      insn->bits3.gen7_dp.last_render_target = 0;
-      insn->bits3.gen7_dp.msg_type = msg_type;
-   } else if (brw->gen == 6) {
-      insn->bits3.gen6_dp.binding_table_index = binding_table_index;
-      insn->bits3.gen6_dp.msg_control = msg_control;
-      insn->bits3.gen6_dp.last_render_target = 0;
-      insn->bits3.gen6_dp.msg_type = msg_type;
-      insn->bits3.gen6_dp.send_commit_msg = 0;
-   } else if (brw->gen == 5) {
-      insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
-      insn->bits3.dp_read_gen5.msg_control = msg_control;
-      insn->bits3.dp_read_gen5.msg_type = msg_type;
-      insn->bits3.dp_read_gen5.target_cache = target_cache;
-   } else if (brw->is_g4x) {
-      insn->bits3.dp_read_g4x.binding_table_index = binding_table_index; /*0:7*/
-      insn->bits3.dp_read_g4x.msg_control = msg_control;  /*8:10*/
-      insn->bits3.dp_read_g4x.msg_type = msg_type;  /*11:13*/
-      insn->bits3.dp_read_g4x.target_cache = target_cache;  /*14:15*/
-   } else {
-      insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/
-      insn->bits3.dp_read.msg_control = msg_control;  /*8:11*/
-      insn->bits3.dp_read.msg_type = msg_type;  /*12:13*/
-      insn->bits3.dp_read.target_cache = target_cache;  /*14:15*/
-   }
+   brw_inst_set_binding_table_index(brw, insn, binding_table_index);
+   brw_inst_set_dp_read_msg_type(brw, insn, msg_type);
+   brw_inst_set_dp_read_msg_control(brw, insn, msg_control);
+   if (brw->gen < 6)
+      brw_inst_set_dp_read_target_cache(brw, insn, target_cache);
 }
 
 void
 brw_set_sampler_message(struct brw_compile *p,
-                        struct brw_instruction *insn,
+                        struct brw_instruction *inst,
                         unsigned binding_table_index,
                         unsigned sampler,
                         unsigned msg_type,
@@ -795,36 +752,49 @@ brw_set_sampler_message(struct brw_compile *p,
 {
    struct brw_context *brw = p->brw;
 
-   brw_set_message_descriptor(p, insn, BRW_SFID_SAMPLER, msg_length,
+   brw_set_message_descriptor(p, inst, BRW_SFID_SAMPLER, msg_length,
 			      response_length, header_present, false);
 
-   if (brw->gen >= 7) {
-      insn->bits3.sampler_gen7.binding_table_index = binding_table_index;
-      insn->bits3.sampler_gen7.sampler = sampler;
-      insn->bits3.sampler_gen7.msg_type = msg_type;
-      insn->bits3.sampler_gen7.simd_mode = simd_mode;
-   } else if (brw->gen >= 5) {
-      insn->bits3.sampler_gen5.binding_table_index = binding_table_index;
-      insn->bits3.sampler_gen5.sampler = sampler;
-      insn->bits3.sampler_gen5.msg_type = msg_type;
-      insn->bits3.sampler_gen5.simd_mode = simd_mode;
-   } else if (brw->is_g4x) {
-      insn->bits3.sampler_g4x.binding_table_index = binding_table_index;
-      insn->bits3.sampler_g4x.sampler = sampler;
-      insn->bits3.sampler_g4x.msg_type = msg_type;
-   } else {
-      insn->bits3.sampler.binding_table_index = binding_table_index;
-      insn->bits3.sampler.sampler = sampler;
-      insn->bits3.sampler.msg_type = msg_type;
-      insn->bits3.sampler.return_format = return_format;
+   brw_inst_set_binding_table_index(brw, inst, binding_table_index);
+   brw_inst_set_sampler(brw, inst, sampler);
+   brw_inst_set_sampler_msg_type(brw, inst, msg_type);
+   if (brw->gen >= 5) {
+      brw_inst_set_sampler_simd_mode(brw, inst, simd_mode);
+   } else if (brw->gen == 4 && !brw->is_g4x) {
+      brw_inst_set_sampler_return_format(brw, inst, return_format);
    }
 }
 
+static void
+gen7_set_dp_scratch_message(struct brw_compile *p,
+                            struct brw_instruction *inst,
+                            bool write,
+                            bool dword,
+                            bool invalidate_after_read,
+                            unsigned num_regs,
+                            unsigned addr_offset,
+                            unsigned mlen,
+                            unsigned rlen,
+                            bool header_present)
+{
+   const struct brw_context *brw = p->brw;
+   assert(num_regs == 1 || num_regs == 2 || num_regs == 4 ||
+          (brw->gen >= 8 && num_regs == 8));
+   brw_set_message_descriptor(p, inst, GEN7_SFID_DATAPORT_DATA_CACHE,
+                              mlen, rlen, header_present, false);
+   brw_inst_set_dp_category(brw, inst, 1); /* Scratch Block Read/Write msgs */
+   brw_inst_set_scratch_read_write(brw, inst, write);
+   brw_inst_set_scratch_type(brw, inst, dword);
+   brw_inst_set_scratch_invalidate_after_read(brw, inst, invalidate_after_read);
+   brw_inst_set_scratch_block_size(brw, inst, ffs(num_regs) - 1);
+   brw_inst_set_scratch_addr_offset(brw, inst, addr_offset);
+}
 
 #define next_insn brw_next_insn
 struct brw_instruction *
 brw_next_insn(struct brw_compile *p, unsigned opcode)
 {
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn;
 
    if (p->nr_insn + 1 > p->store_size) {
@@ -837,7 +807,7 @@ brw_next_insn(struct brw_compile *p, unsigned opcode)
    insn = &p->store[p->nr_insn++];
    memcpy(insn, p->current, sizeof(*insn));
 
-   insn->header.opcode = opcode;
+   brw_inst_set_opcode(brw, insn, opcode);
    return insn;
 }
 
@@ -884,11 +854,11 @@ static struct brw_instruction *brw_alu3(struct brw_compile *p,
 					struct brw_reg src2)
 {
    struct brw_context *brw = p->brw;
-   struct brw_instruction *insn = next_insn(p, opcode);
+   struct brw_instruction *inst = next_insn(p, opcode);
 
    gen7_convert_mrf_to_grf(p, &dest);
 
-   assert(insn->header.access_mode == BRW_ALIGN_16);
+   assert(brw_inst_access_mode(brw, inst) == BRW_ALIGN_16);
 
    assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
 	  dest.file == BRW_MESSAGE_REGISTER_FILE);
@@ -897,42 +867,47 @@ static struct brw_instruction *brw_alu3(struct brw_compile *p,
    assert(dest.type == BRW_REGISTER_TYPE_F ||
           dest.type == BRW_REGISTER_TYPE_D ||
           dest.type == BRW_REGISTER_TYPE_UD);
-   insn->bits1.da3src.dest_reg_file = (dest.file == BRW_MESSAGE_REGISTER_FILE);
-   insn->bits1.da3src.dest_reg_nr = dest.nr;
-   insn->bits1.da3src.dest_subreg_nr = dest.subnr / 16;
-   insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask;
-   guess_execution_size(p, insn, dest);
+   if (brw->gen == 6) {
+      brw_inst_set_3src_dst_reg_file(brw, inst,
+                                     dest.file == BRW_MESSAGE_REGISTER_FILE);
+   }
+   brw_inst_set_3src_dst_reg_nr(brw, inst, dest.nr);
+   brw_inst_set_3src_dst_subreg_nr(brw, inst, dest.subnr / 16);
+   brw_inst_set_3src_dst_writemask(brw, inst, dest.dw1.bits.writemask);
+   guess_execution_size(p, inst, dest);
 
    assert(src0.file == BRW_GENERAL_REGISTER_FILE);
    assert(src0.address_mode == BRW_ADDRESS_DIRECT);
    assert(src0.nr < 128);
-   insn->bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle;
-   insn->bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0);
-   insn->bits2.da3src.src0_reg_nr = src0.nr;
-   insn->bits1.da3src.src0_abs = src0.abs;
-   insn->bits1.da3src.src0_negate = src0.negate;
-   insn->bits2.da3src.src0_rep_ctrl = src0.vstride == BRW_VERTICAL_STRIDE_0;
+   brw_inst_set_3src_src0_swizzle(brw, inst, src0.dw1.bits.swizzle);
+   brw_inst_set_3src_src0_subreg_nr(brw, inst, get_3src_subreg_nr(src0));
+   brw_inst_set_3src_src0_reg_nr(brw, inst, src0.nr);
+   brw_inst_set_3src_src0_abs(brw, inst, src0.abs);
+   brw_inst_set_3src_src0_negate(brw, inst, src0.negate);
+   brw_inst_set_3src_src0_rep_ctrl(brw, inst,
+                                   src0.vstride == BRW_VERTICAL_STRIDE_0);
 
    assert(src1.file == BRW_GENERAL_REGISTER_FILE);
    assert(src1.address_mode == BRW_ADDRESS_DIRECT);
    assert(src1.nr < 128);
-   insn->bits2.da3src.src1_swizzle = src1.dw1.bits.swizzle;
-   insn->bits2.da3src.src1_subreg_nr_low = get_3src_subreg_nr(src1) & 0x3;
-   insn->bits3.da3src.src1_subreg_nr_high = get_3src_subreg_nr(src1) >> 2;
-   insn->bits2.da3src.src1_rep_ctrl = src1.vstride == BRW_VERTICAL_STRIDE_0;
-   insn->bits3.da3src.src1_reg_nr = src1.nr;
-   insn->bits1.da3src.src1_abs = src1.abs;
-   insn->bits1.da3src.src1_negate = src1.negate;
+   brw_inst_set_3src_src1_swizzle(brw, inst, src1.dw1.bits.swizzle);
+   brw_inst_set_3src_src1_subreg_nr(brw, inst, get_3src_subreg_nr(src1));
+   brw_inst_set_3src_src1_reg_nr(brw, inst, src1.nr);
+   brw_inst_set_3src_src1_abs(brw, inst, src1.abs);
+   brw_inst_set_3src_src1_negate(brw, inst, src1.negate);
+   brw_inst_set_3src_src1_rep_ctrl(brw, inst,
+                                   src1.vstride == BRW_VERTICAL_STRIDE_0);
 
    assert(src2.file == BRW_GENERAL_REGISTER_FILE);
    assert(src2.address_mode == BRW_ADDRESS_DIRECT);
    assert(src2.nr < 128);
-   insn->bits3.da3src.src2_swizzle = src2.dw1.bits.swizzle;
-   insn->bits3.da3src.src2_subreg_nr = get_3src_subreg_nr(src2);
-   insn->bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0;
-   insn->bits3.da3src.src2_reg_nr = src2.nr;
-   insn->bits1.da3src.src2_abs = src2.abs;
-   insn->bits1.da3src.src2_negate = src2.negate;
+   brw_inst_set_3src_src2_swizzle(brw, inst, src2.dw1.bits.swizzle);
+   brw_inst_set_3src_src2_subreg_nr(brw, inst, get_3src_subreg_nr(src2));
+   brw_inst_set_3src_src2_reg_nr(brw, inst, src2.nr);
+   brw_inst_set_3src_src2_abs(brw, inst, src2.abs);
+   brw_inst_set_3src_src2_negate(brw, inst, src2.negate);
+   brw_inst_set_3src_src2_rep_ctrl(brw, inst,
+                                   src2.vstride == BRW_VERTICAL_STRIDE_0);
 
    if (brw->gen >= 7) {
       /* Set both the source and destination types based on dest.type,
@@ -943,21 +918,21 @@ static struct brw_instruction *brw_alu3(struct brw_compile *p,
        */
       switch (dest.type) {
       case BRW_REGISTER_TYPE_F:
-         insn->bits1.da3src.src_type = BRW_3SRC_TYPE_F;
-         insn->bits1.da3src.dst_type = BRW_3SRC_TYPE_F;
+         brw_inst_set_3src_src_type(brw, inst, BRW_3SRC_TYPE_F);
+         brw_inst_set_3src_dst_type(brw, inst, BRW_3SRC_TYPE_F);
          break;
       case BRW_REGISTER_TYPE_D:
-         insn->bits1.da3src.src_type = BRW_3SRC_TYPE_D;
-         insn->bits1.da3src.dst_type = BRW_3SRC_TYPE_D;
+         brw_inst_set_3src_src_type(brw, inst, BRW_3SRC_TYPE_D);
+         brw_inst_set_3src_dst_type(brw, inst, BRW_3SRC_TYPE_D);
          break;
       case BRW_REGISTER_TYPE_UD:
-         insn->bits1.da3src.src_type = BRW_3SRC_TYPE_UD;
-         insn->bits1.da3src.dst_type = BRW_3SRC_TYPE_UD;
+         brw_inst_set_3src_src_type(brw, inst, BRW_3SRC_TYPE_UD);
+         brw_inst_set_3src_dst_type(brw, inst, BRW_3SRC_TYPE_UD);
          break;
       }
    }
 
-   return insn;
+   return inst;
 }
 
 
@@ -1025,9 +1000,9 @@ void brw_##OP(struct brw_compile *p,					      \
 									      \
    if (brw->gen < 6) {							      \
       /* turn on round-increments */					      \
-      rnd->header.destreg__conditionalmod = BRW_CONDITIONAL_R;		      \
+      brw_inst_set_cond_modifier(brw, rnd, BRW_CONDITIONAL_R);                \
       add = brw_ADD(p, dest, dest, brw_imm_f(1.0f));			      \
-      add->header.predicate_control = BRW_PREDICATE_NORMAL;		      \
+      brw_inst_set_pred_control(brw, add, BRW_PREDICATE_NORMAL);              \
    }									      \
 }
 
@@ -1171,15 +1146,16 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p,
                                  struct brw_reg index,
                                  unsigned predicate_control)
 {
+   const struct brw_context *brw = p->brw;
    struct brw_reg ip = brw_ip_reg();
-   struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
+   struct brw_instruction *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
 
-   insn->header.execution_size = 1;
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.mask_control = BRW_MASK_DISABLE;
-   insn->header.predicate_control = predicate_control;
+   brw_inst_set_exec_size(brw, inst, BRW_EXECUTE_2);
+   brw_inst_set_qtr_control(brw, inst, BRW_COMPRESSION_NONE);
+   brw_inst_set_mask_control(brw, inst, BRW_MASK_DISABLE);
+   brw_inst_set_pred_control(brw, inst, predicate_control);
 
-   return insn;
+   return inst;
 }
 
 static void
@@ -1253,23 +1229,23 @@ brw_IF(struct brw_compile *p, unsigned execute_size)
       brw_set_src1(p, insn, brw_imm_d(0x0));
    } else if (brw->gen == 6) {
       brw_set_dest(p, insn, brw_imm_w(0));
-      insn->bits1.branch_gen6.jump_count = 0;
+      brw_inst_set_gen6_jump_count(brw, insn, 0);
       brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
       brw_set_src1(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
    } else {
       brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
       brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
       brw_set_src1(p, insn, brw_imm_ud(0));
-      insn->bits3.break_cont.jip = 0;
-      insn->bits3.break_cont.uip = 0;
+      brw_inst_set_jip(brw, insn, 0);
+      brw_inst_set_uip(brw, insn, 0);
    }
 
-   insn->header.execution_size = execute_size;
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.predicate_control = BRW_PREDICATE_NORMAL;
-   insn->header.mask_control = BRW_MASK_ENABLE;
+   brw_inst_set_exec_size(brw, insn, execute_size);
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+   brw_inst_set_pred_control(brw, insn, BRW_PREDICATE_NORMAL);
+   brw_inst_set_mask_control(brw, insn, BRW_MASK_ENABLE);
    if (!p->single_program_flow && brw->gen < 6)
-      insn->header.thread_control = BRW_THREAD_SWITCH;
+      brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
 
    push_if_stack(p, insn);
    p->if_depth_in_loop[p->loop_stack_depth]++;
@@ -1283,23 +1259,21 @@ struct brw_instruction *
 gen6_IF(struct brw_compile *p, uint32_t conditional,
 	struct brw_reg src0, struct brw_reg src1)
 {
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn;
 
    insn = next_insn(p, BRW_OPCODE_IF);
 
    brw_set_dest(p, insn, brw_imm_w(0));
-   if (p->compressed) {
-      insn->header.execution_size = BRW_EXECUTE_16;
-   } else {
-      insn->header.execution_size = BRW_EXECUTE_8;
-   }
-   insn->bits1.branch_gen6.jump_count = 0;
+   brw_inst_set_exec_size(brw, insn, p->compressed ? BRW_EXECUTE_16
+                                                   : BRW_EXECUTE_8);
+   brw_inst_set_gen6_jump_count(brw, insn, 0);
    brw_set_src0(p, insn, src0);
    brw_set_src1(p, insn, src1);
 
-   assert(insn->header.compression_control == BRW_COMPRESSION_NONE);
-   assert(insn->header.predicate_control == BRW_PREDICATE_NONE);
-   insn->header.destreg__conditionalmod = conditional;
+   assert(brw_inst_qtr_control(brw, insn) == BRW_COMPRESSION_NONE);
+   assert(brw_inst_pred_control(brw, insn) == BRW_PREDICATE_NONE);
+   brw_inst_set_cond_modifier(brw, insn, conditional);
 
    push_if_stack(p, insn);
    return insn;
@@ -1313,13 +1287,15 @@ convert_IF_ELSE_to_ADD(struct brw_compile *p,
 		       struct brw_instruction *if_inst,
 		       struct brw_instruction *else_inst)
 {
+   const struct brw_context *brw = p->brw;
+
    /* The next instruction (where the ENDIF would be, if it existed) */
    struct brw_instruction *next_inst = &p->store[p->nr_insn];
 
    assert(p->single_program_flow);
-   assert(if_inst != NULL && if_inst->header.opcode == BRW_OPCODE_IF);
-   assert(else_inst == NULL || else_inst->header.opcode == BRW_OPCODE_ELSE);
-   assert(if_inst->header.execution_size == BRW_EXECUTE_1);
+   assert(if_inst != NULL && brw_inst_opcode(brw, if_inst) == BRW_OPCODE_IF);
+   assert(else_inst == NULL || brw_inst_opcode(brw, else_inst) == BRW_OPCODE_ELSE);
+   assert(brw_inst_exec_size(brw, if_inst) == BRW_EXECUTE_1);
 
    /* Convert IF to an ADD instruction that moves the instruction pointer
     * to the first instruction of the ELSE block.  If there is no ELSE
@@ -1329,19 +1305,19 @@ convert_IF_ELSE_to_ADD(struct brw_compile *p,
     * stack operations, and if we're currently executing, we just want to
     * continue normally.
     */
-   if_inst->header.opcode = BRW_OPCODE_ADD;
-   if_inst->header.predicate_inverse = 1;
+   brw_inst_set_opcode(brw, if_inst, BRW_OPCODE_ADD);
+   brw_inst_set_pred_inv(brw, if_inst, true);
 
    if (else_inst != NULL) {
       /* Convert ELSE to an ADD instruction that points where the ENDIF
        * would be.
        */
-      else_inst->header.opcode = BRW_OPCODE_ADD;
+      brw_inst_set_opcode(brw, else_inst, BRW_OPCODE_ADD);
 
-      if_inst->bits3.ud = (else_inst - if_inst + 1) * 16;
-      else_inst->bits3.ud = (next_inst - else_inst) * 16;
+      brw_inst_set_imm_ud(brw, if_inst, (else_inst - if_inst + 1) * 16);
+      brw_inst_set_imm_ud(brw, else_inst, (next_inst - else_inst) * 16);
    } else {
-      if_inst->bits3.ud = (next_inst - if_inst) * 16;
+      brw_inst_set_imm_ud(brw, if_inst, (next_inst - if_inst) * 16);
    }
 }
 
@@ -1371,9 +1347,9 @@ patch_IF_ELSE(struct brw_compile *p,
    if (brw->gen < 6)
       assert(!p->single_program_flow);
 
-   assert(if_inst != NULL && if_inst->header.opcode == BRW_OPCODE_IF);
+   assert(if_inst != NULL && brw_inst_opcode(brw, if_inst) == BRW_OPCODE_IF);
    assert(endif_inst != NULL);
-   assert(else_inst == NULL || else_inst->header.opcode == BRW_OPCODE_ELSE);
+   assert(else_inst == NULL || brw_inst_opcode(brw, else_inst) == BRW_OPCODE_ELSE);
 
    unsigned br = 1;
    /* Jump count is for 64bit data chunk each, so one 128bit instruction
@@ -1382,8 +1358,8 @@ patch_IF_ELSE(struct brw_compile *p,
    if (brw->gen >= 5)
       br = 2;
 
-   assert(endif_inst->header.opcode == BRW_OPCODE_ENDIF);
-   endif_inst->header.execution_size = if_inst->header.execution_size;
+   assert(brw_inst_opcode(brw, endif_inst) == BRW_OPCODE_ENDIF);
+   brw_inst_set_exec_size(brw, endif_inst, brw_inst_exec_size(brw, if_inst));
 
    if (else_inst == NULL) {
       /* Patch IF -> ENDIF */
@@ -1391,27 +1367,28 @@ patch_IF_ELSE(struct brw_compile *p,
 	 /* Turn it into an IFF, which means no mask stack operations for
 	  * all-false and jumping past the ENDIF.
 	  */
-	 if_inst->header.opcode = BRW_OPCODE_IFF;
-	 if_inst->bits3.if_else.jump_count = br * (endif_inst - if_inst + 1);
-	 if_inst->bits3.if_else.pop_count = 0;
-	 if_inst->bits3.if_else.pad0 = 0;
+         brw_inst_set_opcode(brw, if_inst, BRW_OPCODE_IFF);
+         brw_inst_set_gen4_jump_count(brw, if_inst,
+                                      br * (endif_inst - if_inst + 1));
+         brw_inst_set_gen4_pop_count(brw, if_inst, 0);
       } else if (brw->gen == 6) {
 	 /* As of gen6, there is no IFF and IF must point to the ENDIF. */
-	 if_inst->bits1.branch_gen6.jump_count = br * (endif_inst - if_inst);
+         brw_inst_set_gen6_jump_count(brw, if_inst, br*(endif_inst - if_inst));
       } else {
-	 if_inst->bits3.break_cont.uip = br * (endif_inst - if_inst);
-	 if_inst->bits3.break_cont.jip = br * (endif_inst - if_inst);
+         brw_inst_set_uip(brw, if_inst, br * (endif_inst - if_inst));
+         brw_inst_set_jip(brw, if_inst, br * (endif_inst - if_inst));
       }
    } else {
-      else_inst->header.execution_size = if_inst->header.execution_size;
+      brw_inst_set_exec_size(brw, else_inst, brw_inst_exec_size(brw, if_inst));
 
       /* Patch IF -> ELSE */
       if (brw->gen < 6) {
-	 if_inst->bits3.if_else.jump_count = br * (else_inst - if_inst);
-	 if_inst->bits3.if_else.pop_count = 0;
-	 if_inst->bits3.if_else.pad0 = 0;
+         brw_inst_set_gen4_jump_count(brw, if_inst,
+                                      br * (else_inst - if_inst));
+         brw_inst_set_gen4_pop_count(brw, if_inst, 0);
       } else if (brw->gen == 6) {
-	 if_inst->bits1.branch_gen6.jump_count = br * (else_inst - if_inst + 1);
+         brw_inst_set_gen6_jump_count(brw, if_inst,
+                                      br * (else_inst - if_inst + 1));
       }
 
       /* Patch ELSE -> ENDIF */
@@ -1419,18 +1396,19 @@ patch_IF_ELSE(struct brw_compile *p,
 	 /* BRW_OPCODE_ELSE pre-gen6 should point just past the
 	  * matching ENDIF.
 	  */
-	 else_inst->bits3.if_else.jump_count = br*(endif_inst - else_inst + 1);
-	 else_inst->bits3.if_else.pop_count = 1;
-	 else_inst->bits3.if_else.pad0 = 0;
+         brw_inst_set_gen4_jump_count(brw, else_inst,
+                                      br * (endif_inst - else_inst + 1));
+         brw_inst_set_gen4_pop_count(brw, else_inst, 1);
       } else if (brw->gen == 6) {
 	 /* BRW_OPCODE_ELSE on gen6 should point to the matching ENDIF. */
-	 else_inst->bits1.branch_gen6.jump_count = br*(endif_inst - else_inst);
+         brw_inst_set_gen6_jump_count(brw, else_inst,
+                                      br * (endif_inst - else_inst));
       } else {
 	 /* The IF instruction's JIP should point just past the ELSE */
-	 if_inst->bits3.break_cont.jip = br * (else_inst - if_inst + 1);
+         brw_inst_set_jip(brw, if_inst, br * (else_inst - if_inst + 1));
 	 /* The IF instruction's UIP and ELSE's JIP should point to ENDIF */
-	 if_inst->bits3.break_cont.uip = br * (endif_inst - if_inst);
-	 else_inst->bits3.break_cont.jip = br * (endif_inst - else_inst);
+         brw_inst_set_uip(brw, if_inst, br * (endif_inst - if_inst));
+         brw_inst_set_jip(brw, else_inst, br * (endif_inst - else_inst));
       }
    }
 }
@@ -1449,21 +1427,21 @@ brw_ELSE(struct brw_compile *p)
       brw_set_src1(p, insn, brw_imm_d(0x0));
    } else if (brw->gen == 6) {
       brw_set_dest(p, insn, brw_imm_w(0));
-      insn->bits1.branch_gen6.jump_count = 0;
+      brw_inst_set_gen6_jump_count(brw, insn, 0);
       brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
    } else {
       brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src1(p, insn, brw_imm_ud(0));
-      insn->bits3.break_cont.jip = 0;
-      insn->bits3.break_cont.uip = 0;
+      brw_inst_set_jip(brw, insn, 0);
+      brw_inst_set_uip(brw, insn, 0);
    }
 
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.mask_control = BRW_MASK_ENABLE;
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+   brw_inst_set_mask_control(brw, insn, BRW_MASK_ENABLE);
    if (!p->single_program_flow && brw->gen < 6)
-      insn->header.thread_control = BRW_THREAD_SWITCH;
+      brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
 
    push_if_stack(p, insn);
 }
@@ -1504,7 +1482,7 @@ brw_ENDIF(struct brw_compile *p)
    /* Pop the IF and (optional) ELSE instructions from the stack */
    p->if_depth_in_loop[p->loop_stack_depth]--;
    tmp = pop_if_stack(p);
-   if (tmp->header.opcode == BRW_OPCODE_ELSE) {
+   if (brw_inst_opcode(brw, tmp) == BRW_OPCODE_ELSE) {
       else_inst = tmp;
       tmp = pop_if_stack(p);
    }
@@ -1530,20 +1508,19 @@ brw_ENDIF(struct brw_compile *p)
       brw_set_src1(p, insn, brw_imm_ud(0));
    }
 
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.mask_control = BRW_MASK_ENABLE;
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+   brw_inst_set_mask_control(brw, insn, BRW_MASK_ENABLE);
    if (brw->gen < 6)
-      insn->header.thread_control = BRW_THREAD_SWITCH;
+      brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
 
    /* Also pop item off the stack in the endif instruction: */
    if (brw->gen < 6) {
-      insn->bits3.if_else.jump_count = 0;
-      insn->bits3.if_else.pop_count = 1;
-      insn->bits3.if_else.pad0 = 0;
+      brw_inst_set_gen4_jump_count(brw, insn, 0);
+      brw_inst_set_gen4_pop_count(brw, insn, 1);
    } else if (brw->gen == 6) {
-      insn->bits1.branch_gen6.jump_count = 2;
+      brw_inst_set_gen6_jump_count(brw, insn, 2);
    } else {
-      insn->bits3.break_cont.jip = 2;
+      brw_inst_set_jip(brw, insn, 2);
    }
    patch_IF_ELSE(p, if_inst, else_inst, insn);
 }
@@ -1562,17 +1539,18 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p)
       brw_set_dest(p, insn, brw_ip_reg());
       brw_set_src0(p, insn, brw_ip_reg());
       brw_set_src1(p, insn, brw_imm_d(0x0));
-      insn->bits3.if_else.pad0 = 0;
-      insn->bits3.if_else.pop_count = p->if_depth_in_loop[p->loop_stack_depth];
+      brw_inst_set_gen4_pop_count(brw, insn,
+                                  p->if_depth_in_loop[p->loop_stack_depth]);
    }
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.execution_size = BRW_EXECUTE_8;
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+   brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
 
    return insn;
 }
 
 struct brw_instruction *gen6_CONT(struct brw_compile *p)
 {
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn;
 
    insn = next_insn(p, BRW_OPCODE_CONTINUE);
@@ -1582,28 +1560,30 @@ struct brw_instruction *gen6_CONT(struct brw_compile *p)
    brw_set_src0(p, insn, brw_ip_reg());
    brw_set_src1(p, insn, brw_imm_d(0x0));
 
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.execution_size = BRW_EXECUTE_8;
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+   brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
    return insn;
 }
 
 struct brw_instruction *brw_CONT(struct brw_compile *p)
 {
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn;
    insn = next_insn(p, BRW_OPCODE_CONTINUE);
    brw_set_dest(p, insn, brw_ip_reg());
    brw_set_src0(p, insn, brw_ip_reg());
    brw_set_src1(p, insn, brw_imm_d(0x0));
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-   insn->header.execution_size = BRW_EXECUTE_8;
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+   brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
    /* insn->header.mask_control = BRW_MASK_DISABLE; */
-   insn->bits3.if_else.pad0 = 0;
-   insn->bits3.if_else.pop_count = p->if_depth_in_loop[p->loop_stack_depth];
+   brw_inst_set_gen4_pop_count(brw, insn,
+                               p->if_depth_in_loop[p->loop_stack_depth]);
    return insn;
 }
 
 struct brw_instruction *gen6_HALT(struct brw_compile *p)
 {
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn;
 
    insn = next_insn(p, BRW_OPCODE_HALT);
@@ -1612,10 +1592,10 @@ struct brw_instruction *gen6_HALT(struct brw_compile *p)
    brw_set_src1(p, insn, brw_imm_d(0x0)); /* UIP and JIP, updated later. */
 
    if (p->compressed) {
-      insn->header.execution_size = BRW_EXECUTE_16;
+      brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_16);
    } else {
-      insn->header.compression_control = BRW_COMPRESSION_NONE;
-      insn->header.execution_size = BRW_EXECUTE_8;
+      brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+      brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
    }
    return insn;
 }
@@ -1654,11 +1634,9 @@ struct brw_instruction *brw_DO(struct brw_compile *p, unsigned execute_size)
       brw_set_src0(p, insn, brw_null_reg());
       brw_set_src1(p, insn, brw_null_reg());
 
-      insn->header.compression_control = BRW_COMPRESSION_NONE;
-      insn->header.execution_size = execute_size;
-      insn->header.predicate_control = BRW_PREDICATE_NONE;
-      /* insn->header.mask_control = BRW_MASK_ENABLE; */
-      /* insn->header.mask_control = BRW_MASK_DISABLE; */
+      brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+      brw_inst_set_exec_size(brw, insn, execute_size);
+      brw_inst_set_pred_control(brw, insn, BRW_PREDICATE_NONE);
 
       return insn;
    }
@@ -1684,12 +1662,12 @@ brw_patch_break_cont(struct brw_compile *p, struct brw_instruction *while_inst)
        * been patched because it's part of a loop inside of the one we're
        * patching.
        */
-      if (inst->header.opcode == BRW_OPCODE_BREAK &&
-	  inst->bits3.if_else.jump_count == 0) {
-	 inst->bits3.if_else.jump_count = br * ((while_inst - inst) + 1);
-      } else if (inst->header.opcode == BRW_OPCODE_CONTINUE &&
-		 inst->bits3.if_else.jump_count == 0) {
-	 inst->bits3.if_else.jump_count = br * (while_inst - inst);
+      if (brw_inst_opcode(brw, inst) == BRW_OPCODE_BREAK &&
+          brw_inst_gen4_jump_count(brw, inst) == 0) {
+         brw_inst_set_gen4_jump_count(brw, inst, br*((while_inst - inst) + 1));
+      } else if (brw_inst_opcode(brw, inst) == BRW_OPCODE_CONTINUE &&
+                 brw_inst_gen4_jump_count(brw, inst) == 0) {
+         brw_inst_set_gen4_jump_count(brw, inst, br * (while_inst - inst));
       }
    }
 }
@@ -1710,19 +1688,19 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
       brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src1(p, insn, brw_imm_ud(0));
-      insn->bits3.break_cont.jip = br * (do_insn - insn);
+      brw_inst_set_jip(brw, insn, br * (do_insn - insn));
 
-      insn->header.execution_size = BRW_EXECUTE_8;
+      brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
    } else if (brw->gen == 6) {
       insn = next_insn(p, BRW_OPCODE_WHILE);
       do_insn = get_inner_do_insn(p);
 
       brw_set_dest(p, insn, brw_imm_w(0));
-      insn->bits1.branch_gen6.jump_count = br * (do_insn - insn);
+      brw_inst_set_gen6_jump_count(brw, insn, br * (do_insn - insn));
       brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 
-      insn->header.execution_size = BRW_EXECUTE_8;
+      brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
    } else {
       if (p->single_program_flow) {
 	 insn = next_insn(p, BRW_OPCODE_ADD);
@@ -1731,26 +1709,25 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
 	 brw_set_dest(p, insn, brw_ip_reg());
 	 brw_set_src0(p, insn, brw_ip_reg());
 	 brw_set_src1(p, insn, brw_imm_d((do_insn - insn) * 16));
-	 insn->header.execution_size = BRW_EXECUTE_1;
+         brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_1);
       } else {
 	 insn = next_insn(p, BRW_OPCODE_WHILE);
          do_insn = get_inner_do_insn(p);
 
-	 assert(do_insn->header.opcode == BRW_OPCODE_DO);
+         assert(brw_inst_opcode(brw, do_insn) == BRW_OPCODE_DO);
 
 	 brw_set_dest(p, insn, brw_ip_reg());
 	 brw_set_src0(p, insn, brw_ip_reg());
 	 brw_set_src1(p, insn, brw_imm_d(0));
 
-	 insn->header.execution_size = do_insn->header.execution_size;
-	 insn->bits3.if_else.jump_count = br * (do_insn - insn + 1);
-	 insn->bits3.if_else.pop_count = 0;
-	 insn->bits3.if_else.pad0 = 0;
+         brw_inst_set_exec_size(brw, insn, brw_inst_exec_size(brw, do_insn));
+         brw_inst_set_gen4_jump_count(brw, insn, br * (do_insn - insn + 1));
+         brw_inst_set_gen4_pop_count(brw, insn, 0);
 
 	 brw_patch_break_cont(p, insn);
       }
    }
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
 
    p->loop_stack_depth--;
 
@@ -1768,10 +1745,11 @@ void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx)
    if (brw->gen >= 5)
       jmpi = 2;
 
-   assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI);
-   assert(jmp_insn->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE);
+   assert(brw_inst_opcode(brw, jmp_insn) == BRW_OPCODE_JMPI);
+   assert(brw_inst_src1_reg_file(brw, jmp_insn) == BRW_IMMEDIATE_VALUE);
 
-   jmp_insn->bits3.ud = jmpi * (p->nr_insn - jmp_insn_idx - 1);
+   brw_inst_set_gen4_jump_count(brw, jmp_insn,
+                                jmpi * (p->nr_insn - jmp_insn_idx - 1));
 }
 
 /* To integrate with the above, it makes sense that the comparison
@@ -1787,7 +1765,7 @@ void brw_CMP(struct brw_compile *p,
    struct brw_context *brw = p->brw;
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
 
-   insn->header.destreg__conditionalmod = conditional;
+   brw_inst_set_cond_modifier(brw, insn, conditional);
    brw_set_dest(p, insn, dest);
    brw_set_src0(p, insn, src0);
    brw_set_src1(p, insn, src1);
@@ -1802,7 +1780,7 @@ void brw_CMP(struct brw_compile *p,
    if (brw->gen == 7) {
       if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
           dest.nr == BRW_ARF_NULL) {
-         insn->header.thread_control = BRW_THREAD_SWITCH;
+         brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
       }
    }
 }
@@ -1829,8 +1807,8 @@ void gen4_math(struct brw_compile *p,
    /* Example code doesn't set predicate_control for send
     * instructions.
     */
-   insn->header.predicate_control = 0;
-   insn->header.destreg__conditionalmod = msg_reg_nr;
+   brw_inst_set_pred_control(brw, insn, 0);
+   brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
 
    brw_set_dest(p, insn, dest);
    brw_set_src0(p, insn, src);
@@ -1888,10 +1866,7 @@ void gen6_math(struct brw_compile *p,
       assert(!src1.abs);
    }
 
-   /* Math is the same ISA format as other opcodes, except that CondModifier
-    * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
-    */
-   insn->header.destreg__conditionalmod = function;
+   brw_inst_set_math_function(brw, insn, function);
 
    brw_set_dest(p, insn, dest);
    brw_set_src0(p, insn, src0);
@@ -1957,12 +1932,13 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
       struct brw_reg src_header = retype(brw_vec8_grf(0, 0),
 					 BRW_REGISTER_TYPE_UW);
 
-      if (insn->header.compression_control != BRW_COMPRESSION_NONE) {
-	 insn->header.compression_control = BRW_COMPRESSION_NONE;
+      if (brw_inst_qtr_control(brw, insn) != BRW_COMPRESSION_NONE) {
+         brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
 	 src_header = vec16(src_header);
       }
-      assert(insn->header.predicate_control == BRW_PREDICATE_NONE);
-      insn->header.destreg__conditionalmod = mrf.nr;
+      assert(brw_inst_pred_control(brw, insn) == BRW_PREDICATE_NONE);
+      if (brw->gen < 6)
+         brw_inst_set_base_mrf(brw, insn, mrf.nr);
 
       /* Until gen6, writes followed by reads from the same location
        * are not guaranteed to be ordered unless write_commit is set.
@@ -2061,15 +2037,15 @@ brw_oword_block_read_scratch(struct brw_compile *p,
    {
       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
 
-      assert(insn->header.predicate_control == 0);
-      insn->header.compression_control = BRW_COMPRESSION_NONE;
-      insn->header.destreg__conditionalmod = mrf.nr;
+      assert(brw_inst_pred_control(brw, insn) == 0);
+      brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
 
       brw_set_dest(p, insn, dest);	/* UW? */
       if (brw->gen >= 6) {
 	 brw_set_src0(p, insn, mrf);
       } else {
 	 brw_set_src0(p, insn, brw_null_reg());
+         brw_inst_set_base_mrf(brw, insn, mrf.nr);
       }
 
       brw_set_dp_read_message(p,
@@ -2090,40 +2066,34 @@ gen7_block_read_scratch(struct brw_compile *p,
                         int num_regs,
                         unsigned offset)
 {
-   dest = retype(dest, BRW_REGISTER_TYPE_UW);
-
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+   assert(brw_inst_pred_control(brw, insn) == BRW_PREDICATE_NONE);
 
-   assert(insn->header.predicate_control == BRW_PREDICATE_NONE);
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
-
-   brw_set_dest(p, insn, dest);
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
+   brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UW));
 
    /* The HW requires that the header is present; this is to get the g0.5
     * scratch offset.
     */
-   bool header_present = true;
    brw_set_src0(p, insn, brw_vec8_grf(0, 0));
 
-   brw_set_message_descriptor(p, insn,
-                              GEN7_SFID_DATAPORT_DATA_CACHE,
-                              1, /* mlen: just g0 */
-                              num_regs,
-                              header_present,
-                              false);
-
-   insn->bits3.ud |= GEN7_DATAPORT_SCRATCH_READ;
-
-   assert(num_regs == 1 || num_regs == 2 || num_regs == 4);
-   insn->bits3.ud |= (num_regs - 1) << GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT;
-
    /* According to the docs, offset is "A 12-bit HWord offset into the memory
     * Immediate Memory buffer as specified by binding table 0xFF."  An HWORD
     * is 32 bytes, which happens to be the size of a register.
     */
    offset /= REG_SIZE;
    assert(offset < (1 << 12));
-   insn->bits3.ud |= offset;
+
+   gen7_set_dp_scratch_message(p, insn,
+                               false, /* scratch read */
+                               false, /* OWords */
+                               false, /* invalidate after read */
+                               num_regs,
+                               offset,
+                               1,        /* mlen: just g0 */
+                               num_regs, /* rlen */
+                               true);    /* header present */
 }
 
 /**
@@ -2160,7 +2130,6 @@ void brw_oword_block_read(struct brw_compile *p,
 	   brw_imm_ud(offset));
 
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
-   insn->header.destreg__conditionalmod = mrf.nr;
 
    /* cast dest to a uword[8] vector */
    dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
@@ -2170,6 +2139,7 @@ void brw_oword_block_read(struct brw_compile *p,
       brw_set_src0(p, insn, mrf);
    } else {
       brw_set_src0(p, insn, brw_null_reg());
+      brw_inst_set_base_mrf(brw, insn, mrf.nr);
    }
 
    brw_set_dp_read_message(p,
@@ -2212,7 +2182,7 @@ void brw_fb_WRITE(struct brw_compile *p,
    } else {
       insn = next_insn(p, BRW_OPCODE_SEND);
    }
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
+   brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
 
    if (brw->gen >= 6) {
       /* headerless version, just submit color payload */
@@ -2220,7 +2190,7 @@ void brw_fb_WRITE(struct brw_compile *p,
 
       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
    } else {
-      insn->header.destreg__conditionalmod = msg_reg_nr;
+      brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
 
       msg_type = BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
    }
@@ -2266,7 +2236,7 @@ void brw_SAMPLE(struct brw_compile *p,
       gen6_resolve_implied_move(p, &src0, msg_reg_nr);
 
    insn = next_insn(p, BRW_OPCODE_SEND);
-   insn->header.predicate_control = 0; /* XXX */
+   brw_inst_set_pred_control(brw, insn, BRW_PREDICATE_NONE); /* XXX */
 
    /* From the 965 PRM (volume 4, part 1, section 14.2.41):
     *
@@ -2280,11 +2250,11 @@ void brw_SAMPLE(struct brw_compile *p,
     * are allowed in SIMD16 mode and they could not work without SecHalf.  For
     * these reasons, we allow BRW_COMPRESSION_2NDHALF here.
     */
-   if (insn->header.compression_control != BRW_COMPRESSION_2NDHALF)
-      insn->header.compression_control = BRW_COMPRESSION_NONE;
+   if (brw_inst_qtr_control(brw, insn) != BRW_COMPRESSION_2NDHALF)
+      brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
 
    if (brw->gen < 6)
-      insn->header.destreg__conditionalmod = msg_reg_nr;
+      brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
 
    brw_set_dest(p, insn, dest);
    brw_set_src0(p, insn, src0);
@@ -2339,7 +2309,7 @@ void brw_urb_WRITE(struct brw_compile *p,
    brw_set_src1(p, insn, brw_imm_d(0));
 
    if (brw->gen < 6)
-      insn->header.destreg__conditionalmod = msg_reg_nr;
+      brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
 
    brw_set_urb_message(p,
 		       insn,
@@ -2362,7 +2332,7 @@ brw_find_next_block_end(struct brw_compile *p, int start_offset)
         offset = next_offset(brw, store, offset)) {
       struct brw_instruction *insn = store + offset;
 
-      switch (insn->header.opcode) {
+      switch (brw_inst_opcode(brw, insn)) {
       case BRW_OPCODE_ENDIF:
       case BRW_OPCODE_ELSE:
       case BRW_OPCODE_WHILE:
@@ -2394,9 +2364,9 @@ brw_find_loop_end(struct brw_compile *p, int start_offset)
         offset = next_offset(brw, store, offset)) {
       struct brw_instruction *insn = store + offset;
 
-      if (insn->header.opcode == BRW_OPCODE_WHILE) {
-	 int jip = brw->gen == 6 ? insn->bits1.branch_gen6.jump_count
-				   : insn->bits3.break_cont.jip;
+      if (brw_inst_opcode(brw, insn) == BRW_OPCODE_WHILE) {
+         int jip = brw->gen == 6 ? brw_inst_gen6_jump_count(brw, insn)
+                                 : brw_inst_jip(brw, insn);
 	 if (offset + jip * scale <= start_offset)
 	    return offset;
       }
@@ -2423,39 +2393,39 @@ brw_set_uip_jip(struct brw_compile *p)
         offset = next_offset(brw, store, offset)) {
       struct brw_instruction *insn = store + offset;
 
-      if (insn->header.cmpt_control) {
+      if (brw_inst_cmpt_control(brw, insn)) {
 	 /* Fixups for compacted BREAK/CONTINUE not supported yet. */
-	 assert(insn->header.opcode != BRW_OPCODE_BREAK &&
-		insn->header.opcode != BRW_OPCODE_CONTINUE &&
-		insn->header.opcode != BRW_OPCODE_HALT);
+         assert(brw_inst_opcode(brw, insn) != BRW_OPCODE_BREAK &&
+                brw_inst_opcode(brw, insn) != BRW_OPCODE_CONTINUE &&
+                brw_inst_opcode(brw, insn) != BRW_OPCODE_HALT);
 	 continue;
       }
 
       int block_end_offset = brw_find_next_block_end(p, offset);
-      switch (insn->header.opcode) {
+      switch (brw_inst_opcode(brw, insn)) {
       case BRW_OPCODE_BREAK:
          assert(block_end_offset != 0);
-	 insn->bits3.break_cont.jip = (block_end_offset - offset) / scale;
+         brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
 	 /* Gen7 UIP points to WHILE; Gen6 points just after it */
-	 insn->bits3.break_cont.uip =
+         brw_inst_set_uip(brw, insn,
 	    (brw_find_loop_end(p, offset) - offset +
-             (brw->gen == 6 ? 16 : 0)) / scale;
+             (brw->gen == 6 ? 16 : 0)) / scale);
 	 break;
       case BRW_OPCODE_CONTINUE:
          assert(block_end_offset != 0);
-	 insn->bits3.break_cont.jip = (block_end_offset - offset) / scale;
-	 insn->bits3.break_cont.uip =
-            (brw_find_loop_end(p, offset) - offset) / scale;
+         brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
+         brw_inst_set_uip(brw, insn,
+            (brw_find_loop_end(p, offset) - offset) / scale);
 
-	 assert(insn->bits3.break_cont.uip != 0);
-	 assert(insn->bits3.break_cont.jip != 0);
+         assert(brw_inst_uip(brw, insn) != 0);
+         assert(brw_inst_jip(brw, insn) != 0);
 	 break;
 
       case BRW_OPCODE_ENDIF:
          if (block_end_offset == 0)
-            insn->bits3.break_cont.jip = 2;
+            brw_inst_set_jip(brw, insn, 2);
          else
-            insn->bits3.break_cont.jip = (block_end_offset - offset) / scale;
+            brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
 	 break;
 
       case BRW_OPCODE_HALT:
@@ -2471,12 +2441,12 @@ brw_set_uip_jip(struct brw_compile *p)
 	  * instruction.
 	  */
 	 if (block_end_offset == 0) {
-	    insn->bits3.break_cont.jip = insn->bits3.break_cont.uip;
+            brw_inst_set_jip(brw, insn, brw_inst_uip(brw, insn));
 	 } else {
-	    insn->bits3.break_cont.jip = (block_end_offset - offset) / scale;
+            brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
 	 }
-	 assert(insn->bits3.break_cont.uip != 0);
-	 assert(insn->bits3.break_cont.jip != 0);
+         assert(brw_inst_uip(brw, insn) != 0);
+         assert(brw_inst_jip(brw, insn) != 0);
 	 break;
       }
    }
@@ -2501,7 +2471,7 @@ void brw_ff_sync(struct brw_compile *p,
    brw_set_src1(p, insn, brw_imm_d(0));
 
    if (brw->gen < 6)
-      insn->header.destreg__conditionalmod = msg_reg_nr;
+      brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
 
    brw_set_ff_sync_message(p,
 			   insn,
@@ -2558,38 +2528,41 @@ brw_set_dp_untyped_atomic_message(struct brw_compile *p,
                                   unsigned response_length,
                                   bool header_present)
 {
-   if (p->brw->is_haswell) {
+   const struct brw_context *brw = p->brw;
+
+   unsigned msg_control =
+      atomic_op | /* Atomic Operation Type: BRW_AOP_* */
+      (response_length ? 1 << 5 : 0); /* Return data expected */
+
+   if (brw->is_haswell) {
       brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
                                  msg_length, response_length,
                                  header_present, false);
 
 
-      if (insn->header.access_mode == BRW_ALIGN_1) {
-         if (insn->header.execution_size != BRW_EXECUTE_16)
-            insn->bits3.ud |= 1 << 12; /* SIMD8 mode */
+      if (brw_inst_access_mode(brw, insn) == BRW_ALIGN_1) {
+         if (brw_inst_exec_size(brw, insn) != BRW_EXECUTE_16)
+            msg_control |= 1 << 4; /* SIMD8 mode */
 
-         insn->bits3.gen7_dp.msg_type =
-            HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
+         brw_inst_set_dp_msg_type(brw, insn,
+                                  HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP);
       } else {
-         insn->bits3.gen7_dp.msg_type =
-            HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
+         brw_inst_set_dp_msg_type(brw, insn,
+            HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2);
       }
    } else {
       brw_set_message_descriptor(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
                                  msg_length, response_length,
                                  header_present, false);
 
-      insn->bits3.gen7_dp.msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
+      brw_inst_set_dp_msg_type(brw, insn, GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP);
 
-      if (insn->header.execution_size != BRW_EXECUTE_16)
-         insn->bits3.ud |= 1 << 12; /* SIMD8 mode */
+      if (brw_inst_exec_size(brw, insn) != BRW_EXECUTE_16)
+         msg_control |= 1 << 4; /* SIMD8 mode */
    }
 
-   if (response_length)
-      insn->bits3.ud |= 1 << 13; /* Return data expected */
-
-   insn->bits3.gen7_dp.binding_table_index = bind_table_index;
-   insn->bits3.ud |= atomic_op << 8;
+   brw_inst_set_binding_table_index(brw, insn, bind_table_index);
+   brw_inst_set_dp_msg_control(brw, insn, msg_control);
 }
 
 void
@@ -2600,6 +2573,7 @@ brw_untyped_atomic(struct brw_compile *p,
                    unsigned bind_table_index,
                    unsigned msg_length,
                    unsigned response_length) {
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
 
    brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
@@ -2607,7 +2581,7 @@ brw_untyped_atomic(struct brw_compile *p,
    brw_set_src1(p, insn, brw_imm_d(0));
    brw_set_dp_untyped_atomic_message(
       p, insn, atomic_op, bind_table_index, msg_length, response_length,
-      insn->header.access_mode == BRW_ALIGN_1);
+      brw_inst_access_mode(brw, insn) == BRW_ALIGN_1);
 }
 
 static void
@@ -2618,35 +2592,39 @@ brw_set_dp_untyped_surface_read_message(struct brw_compile *p,
                                         unsigned response_length,
                                         bool header_present)
 {
+   const struct brw_context *brw = p->brw;
    const unsigned dispatch_width =
-      (insn->header.execution_size == BRW_EXECUTE_16 ? 16 : 8);
+      (brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16 ? 16 : 8);
    const unsigned num_channels = response_length / (dispatch_width / 8);
 
-   if (p->brw->is_haswell) {
+   if (brw->is_haswell) {
       brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
                                  msg_length, response_length,
                                  header_present, false);
 
-      insn->bits3.gen7_dp.msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
+      brw_inst_set_dp_msg_type(brw, insn,
+                               HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ);
    } else {
       brw_set_message_descriptor(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
                                  msg_length, response_length,
                                  header_present, false);
 
-      insn->bits3.gen7_dp.msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
+      brw_inst_set_dp_msg_type(brw, insn,
+                               GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ);
    }
 
-   if (insn->header.access_mode == BRW_ALIGN_1) {
+   /* Set mask of 32-bit channels to drop. */
+   unsigned msg_control = (0xf & (0xf << num_channels));
+
+   if (brw_inst_access_mode(brw, insn) == BRW_ALIGN_1) {
       if (dispatch_width == 16)
-         insn->bits3.ud |= 1 << 12; /* SIMD16 mode */
+         msg_control |= 1 << 4; /* SIMD16 mode */
       else
-         insn->bits3.ud |= 2 << 12; /* SIMD8 mode */
+         msg_control |= 2 << 4; /* SIMD8 mode */
    }
 
-   insn->bits3.gen7_dp.binding_table_index = bind_table_index;
-
-   /* Set mask of 32-bit channels to drop. */
-   insn->bits3.ud |= (0xf & (0xf << num_channels)) << 8;
+   brw_inst_set_binding_table_index(brw, insn, bind_table_index);
+   brw_inst_set_dp_msg_control(brw, insn, msg_control);
 }
 
 void
@@ -2657,13 +2635,14 @@ brw_untyped_surface_read(struct brw_compile *p,
                          unsigned msg_length,
                          unsigned response_length)
 {
+   const struct brw_context *brw = p->brw;
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
 
    brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
    brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD));
    brw_set_dp_untyped_surface_read_message(
       p, insn, bind_table_index, msg_length, response_length,
-      insn->header.access_mode == BRW_ALIGN_1);
+      brw_inst_access_mode(brw, insn) == BRW_ALIGN_1);
 }
 
 /**