diff options
| author | Ilia Mirkin <[email protected]> | 2015-07-23 02:27:04 -0400 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2015-07-23 03:33:09 -0400 |
| commit | 77672cdb64e9c19e974fe5985050709fc317498e (patch) | |
| tree | 5a3e3419c95359d0f0cd6ee4ddddda7924281d28 | |
| parent | 7cf2bffe8254de6808202d866598ec4c9afe1a51 (diff) | |
nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argument
Apparently a multi-word load can potentially overwrite the indirect
sources, so make sure that RA picks different registers for those.
Signed-off-by: Ilia Mirkin <[email protected]>
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp index 898653c9953..78bc97f4397 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp @@ -2066,6 +2066,8 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb) condenseDefs(i); if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8) addHazard(i, i->src(0).getIndirect(0)); + if (i->src(0).isIndirect(1) && typeSizeof(i->dType) >= 8) + addHazard(i, i->src(0).getIndirect(1)); } else if (i->op == OP_UNION || i->op == OP_MERGE || |