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authorJason Ekstrand <[email protected]>2016-03-01 10:59:21 -0800
committerJason Ekstrand <[email protected]>2016-03-01 11:03:29 -0800
commit6e20c1e058d7449c800506d05cd1c6431fa77a4b (patch)
treee66c5dbb8a3c6f7fdb841b9058c3a75df318c6ac
parent4cfdd1650083f3e425112ff697538e9818bc8946 (diff)
anv/cmd_buffer: Look at both sides for stencil enable
Now it's all consistent with gen9
-rw-r--r--src/intel/vulkan/gen7_cmd_buffer.c6
-rw-r--r--src/intel/vulkan/gen8_cmd_buffer.c4
2 files changed, 4 insertions, 6 deletions
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c
index 09025ef2323..3ed93137f6a 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -586,11 +586,9 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
- const struct anv_image_view *iview =
- anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
-
struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
- .StencilBufferWriteEnable = iview && (iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT),
+ .StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
+ d->stencil_write_mask.back != 0,
.StencilTestMask = d->stencil_compare_mask.front & 0xff,
.StencilWriteMask = d->stencil_write_mask.front & 0xff,
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c
index 8a0fe60db33..884152da207 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -388,8 +388,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
GENX(3DSTATE_WM_DEPTH_STENCIL_header),
- /* Is this what we need to do? */
- .StencilBufferWriteEnable = d->stencil_write_mask.front != 0,
+ .StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
+ d->stencil_write_mask.back != 0,
.StencilTestMask = d->stencil_compare_mask.front & 0xff,
.StencilWriteMask = d->stencil_write_mask.front & 0xff,