diff options
| author | Marek Olšák <[email protected]> | 2016-10-15 16:09:26 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | 6e0d64712aa3fdf07060eeda52417143514004e5 (patch) | |
| tree | bc7e3b3e47e86feee850df15104cf94064faa4a1 | |
| parent | 81aa21d7328b26c70d5220b515d3dd293ce2851d (diff) | |
radeonsi/gfx9: use ACQUIRE_MEM
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index f01ac01b383..a80f021d64b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -754,12 +754,23 @@ static void si_emit_surface_sync(struct r600_common_context *rctx, { struct radeon_winsys_cs *cs = rctx->gfx.cs; - /* ACQUIRE_MEM is only required on a compute ring. */ - radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); - radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ - radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ - radeon_emit(cs, 0); /* CP_COHER_BASE */ - radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ + if (rctx->chip_class >= GFX9) { + /* Flush caches and wait for the caches to assert idle. */ + radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0)); + radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ + radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ + radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */ + radeon_emit(cs, 0); /* CP_COHER_BASE */ + radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ + radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ + } else { + /* ACQUIRE_MEM is only required on a compute ring. */ + radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); + radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ + radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ + radeon_emit(cs, 0); /* CP_COHER_BASE */ + radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ + } } void si_emit_cache_flush(struct si_context *sctx) |