diff options
| author | Kenneth Graunke <[email protected]> | 2016-05-08 21:15:04 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2016-05-09 16:20:18 -0700 |
| commit | 5ce405ba0ffd44653b2cdf96fefdad30d218e224 (patch) | |
| tree | fa4da77308ec94521f7ac6b5e1cad0946847881d | |
| parent | e0e7280db0b03b08479ef9db681db186f80605e5 (diff) | |
i965: Actually assign binding table offsets for the TCS.
As far as I can tell, this was just entirely missing...honestly, I'm
not sure how anything worked at all.
Caught by noticing GPU hangs in image load store tests with scalar TCS,
but probably has broader implications.
Cc: [email protected]
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Kristian Høgsberg <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tcs.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c index 98ed2b253a6..e8178c6daab 100644 --- a/src/mesa/drivers/dri/i965/brw_tcs.c +++ b/src/mesa/drivers/dri/i965/brw_tcs.c @@ -168,6 +168,7 @@ brw_codegen_tcs_prog(struct brw_context *brw, { struct gl_context *ctx = &brw->ctx; const struct brw_compiler *compiler = brw->intelScreen->compiler; + const struct brw_device_info *devinfo = compiler->devinfo; struct brw_stage_state *stage_state = &brw->tcs.base; nir_shader *nir; struct brw_tcs_prog_data prog_data; @@ -209,6 +210,10 @@ brw_codegen_tcs_prog(struct brw_context *brw, prog_data.base.base.nr_params = param_count; if (tcs) { + brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL, devinfo, + shader_prog, &tcp->program.Base, + &prog_data.base.base, 0); + prog_data.base.base.image_param = rzalloc_array(NULL, struct brw_image_param, tcs->NumImages); prog_data.base.base.nr_image_params = tcs->NumImages; |