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authorChia-I Wu <olvaffe@gmail.com>2014-03-10 12:40:29 +0800
committerChia-I Wu <olvaffe@gmail.com>2014-03-10 16:42:42 +0800
commit345bf92f130e4dc9f36b848af0e7878d7fb5e3cb (patch)
treeb92f2c365b88b46ccf0553cd88a32b5db60c49fb
parent747627d0456eb14b2fb4c320c5bf0f084f3b2907 (diff)
ilo: print a warning when PPGTT is disabled
Despite what the PRMs say, the driver appears to work fine when PPGTT is disabled. But at least print a warning in that case.
-rw-r--r--src/gallium/drivers/ilo/ilo_common.h1
-rw-r--r--src/gallium/drivers/ilo/ilo_screen.c19
-rw-r--r--src/gallium/winsys/intel/drm/intel_drm_winsys.c3
-rw-r--r--src/gallium/winsys/intel/intel_winsys.h1
4 files changed, 24 insertions, 0 deletions
diff --git a/src/gallium/drivers/ilo/ilo_common.h b/src/gallium/drivers/ilo/ilo_common.h
index db7fdc7f1fa..dd31f749bbf 100644
--- a/src/gallium/drivers/ilo/ilo_common.h
+++ b/src/gallium/drivers/ilo/ilo_common.h
@@ -72,6 +72,7 @@ struct ilo_dev_info {
bool has_llc;
bool has_address_swizzling;
bool has_logical_context;
+ bool has_ppgtt;
bool has_timestamp;
bool has_gen7_sol_reset;
diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c
index 5d652e4ad73..442e704615d 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -652,6 +652,7 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
dev->has_llc = info->has_llc;
dev->has_address_swizzling = info->has_address_swizzling;
dev->has_logical_context = info->has_logical_context;
+ dev->has_ppgtt = info->has_ppgtt;
dev->has_timestamp = info->has_timestamp;
dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
@@ -661,6 +662,24 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
}
/*
+ * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
+ * writes on GEN6.
+ *
+ * From the Sandy Bridge PRM, volume 1 part 3, page 101:
+ *
+ * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
+ * code is in a secure environment, independent of address space.
+ * Under this condition, this bit only specifies the address space
+ * (GGTT or PPGTT). All commands are executed "as-is""
+ *
+ * We need PPGTT to be enabled on GEN6 too.
+ */
+ if (!dev->has_ppgtt) {
+ /* experiments show that it does not really matter... */
+ ilo_warn("PPGTT disabled\n");
+ }
+
+ /*
* From the Sandy Bridge PRM, volume 4 part 2, page 18:
*
* "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
index dfef9f4a914..250b36f524b 100644
--- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
+++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
@@ -149,6 +149,9 @@ probe_winsys(struct intel_winsys *winsys)
winsys->first_gem_ctx = drm_intel_gem_context_create(winsys->bufmgr);
info->has_logical_context = (winsys->first_gem_ctx != NULL);
+ get_param(winsys, I915_PARAM_HAS_ALIASING_PPGTT, &val);
+ info->has_ppgtt = val;
+
/* test TIMESTAMP read */
info->has_timestamp = test_reg_read(winsys, 0x2358);
diff --git a/src/gallium/winsys/intel/intel_winsys.h b/src/gallium/winsys/intel/intel_winsys.h
index 3c9e6f267be..6571719d113 100644
--- a/src/gallium/winsys/intel/intel_winsys.h
+++ b/src/gallium/winsys/intel/intel_winsys.h
@@ -73,6 +73,7 @@ struct intel_winsys_info {
bool has_llc;
bool has_address_swizzling;
bool has_logical_context;
+ bool has_ppgtt;
/* valid registers for intel_winsys_read_reg() */
bool has_timestamp;