diff options
| author | Eric Anholt <[email protected]> | 2010-10-19 09:44:20 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2010-10-19 10:48:56 -0700 |
| commit | 32573792de559c4dbad766a7cfcf02ea71f5047f (patch) | |
| tree | c774b8d2f3e32bdfcdea052f77f43910c6289463 | |
| parent | 36dde032a4f7d6a8b68c1adc8e829816e2e8826e (diff) | |
i965: Tell the shader compiler when we expect depth writes for gen6.
This fixes hangs in some Z-writes-in-shaders tests, though other
pieces don't come out correctly.
Bug #30392: hang in fbo-fblit-d24s8. (still fails with bad color drawn
to some targets)
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 7aad6caf719..f2ce7565643 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -318,6 +318,12 @@ static void brw_wm_populate_key( struct brw_context *brw, /* R31: MSAA position offsets. */ /* R32-: bary for 32-pixel. */ /* R58-59: interp W for 32-pixel. */ + + if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { + key->source_depth_to_render_target = GL_TRUE; + key->computes_depth = GL_TRUE; + } + } else { brw_wm_lookup_iz(intel, line_aa, |