diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-01 15:45:11 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-02 13:34:43 +0200 |
| commit | 10d08da52c666e5158339da9dfc4e8c411e252ea (patch) | |
| tree | 546c9d4a95db1be02ae38f831ef750f736626585 | |
| parent | 9c9745e8ddf2bf22dca8cd380200ddf011343364 (diff) | |
radv/gfx10: add missing dcc_tile_swizzle tweak
Fixes: c90f46700dd ("radv/gfx10: mask DCC tile swizzle by alignment")
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index ce12bb61fb9..aaaf15ec8dc 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -484,7 +484,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (chip_class <= GFX8) meta_va += base_level_info->dcc_offset; - meta_va |= (uint32_t)plane->surface.tile_swizzle << 8; + unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8; + dcc_tile_swizzle &= plane->surface.dcc_alignment - 1; + meta_va |= dcc_tile_swizzle; } else if (!is_storage_image && radv_image_is_tc_compat_htile(image)) { meta_va = gpu_address + image->htile_offset; |