nv50: flag to indicate to winsys we want a surface for use as a zeta buffer

NVIDIA love to make life difficult.. we need different flags in PTEs for
zeta.. yay.. not.

5 files changed, 29 insertions, 3 deletions

diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h b/src/gallium/drivers/nouveau/nouveau_winsys.h
index 07a41dcf4a1..13810460bfe 100644
--- a/src/gallium/drivers/nouveau/nouveau_winsys.h
+++ b/src/gallium/drivers/nouveau/nouveau_winsys.h
@@ -18,6 +18,7 @@
 #define NOUVEAU_CAP_HW_IDXBUF (0xbeef0001)
 
 #define NOUVEAU_BUFFER_USAGE_TEXTURE (1 << 16)
+#define NOUVEAU_BUFFER_USAGE_ZETA    (1 << 17)
 
 struct nouveau_winsys {
 	struct nouveau_context *nv;
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c b/src/gallium/drivers/nv50/nv50_miptree.c
index be85c3fd5ce..459e0ff9dd6 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -21,6 +21,7 @@ nv50_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
 {
 	struct pipe_winsys *ws = pscreen->winsys;
 	struct nv50_miptree *mt = CALLOC_STRUCT(nv50_miptree);
+	unsigned usage;
 
 	NOUVEAU_ERR("unimplemented\n");
 
@@ -28,7 +29,17 @@ nv50_miptree_create(struct pipe_screen *pscreen, const struct pipe_texture *pt)
 	mt->base.refcount = 1;
 	mt->base.screen = pscreen;
 
-	mt->buffer = ws->buffer_create(ws, 256, PIPE_BUFFER_USAGE_PIXEL,
+	usage = PIPE_BUFFER_USAGE_PIXEL;
+	switch (pt->format) {
+	case PIPE_FORMAT_Z24S8_UNORM:
+	case PIPE_FORMAT_Z16_UNORM:
+		usage |= NOUVEAU_BUFFER_USAGE_ZETA;
+		break;
+	default:
+		break;
+	}
+
+	mt->buffer = ws->buffer_create(ws, 256, usage,
 				       pt->width[0] * pt->cpp * pt->height[0]);
 	if (!mt->buffer) {
 		FREE(mt);
diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c
index 5f10fe2e440..d76cce9f791 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -284,6 +284,10 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
 		so_data  (so, 0xffffffff);
 	}
 
+	so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR, 2);
+	so_data  (so, fui(0.0));
+	so_data  (so, fui(1.0));
+
 	so_emit(nvws, so);
 	so_ref(NULL, &so);
 	nvws->push_flush(nvws, 0, NULL);
diff --git a/src/gallium/drivers/nv50/nv50_state.c b/src/gallium/drivers/nv50/nv50_state.c
index b56a3992bc4..176ebff5da4 100644
--- a/src/gallium/drivers/nv50/nv50_state.c
+++ b/src/gallium/drivers/nv50/nv50_state.c
@@ -247,8 +247,8 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe,
 	struct nouveau_stateobj *so = so_new(64, 0);
 
 	so_method(so, tesla, NV50TCL_DEPTH_WRITE_ENABLE, 1);
-	so_data  (so, 0); //cso->depth.writemask ? 1 : 0);
-	if (0 && cso->depth.enabled) {
+	so_data  (so, cso->depth.writemask ? 1 : 0);
+	if (cso->depth.enabled) {
 		so_method(so, tesla, NV50TCL_DEPTH_TEST_ENABLE, 1);
 		so_data  (so, 1);
 		so_method(so, tesla, NV50TCL_DEPTH_TEST_FUNC, 1);
diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c b/src/gallium/drivers/nv50/nv50_state_validate.c
index 5f2244e3e80..a3f399a139f 100644
--- a/src/gallium/drivers/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nv50/nv50_state_validate.c
@@ -70,6 +70,9 @@ nv50_state_validate_fb(struct nv50_context *nv50)
 		case PIPE_FORMAT_Z24S8_UNORM:
 			so_data(so, 0x16);
 			break;
+		case PIPE_FORMAT_Z16_UNORM:
+			so_data(so, 0x15);
+			break;
 		default:
 			{
 				char fmt[128];
@@ -81,6 +84,13 @@ nv50_state_validate_fb(struct nv50_context *nv50)
 		}
 		so_data(so, 0x00000040);
 		so_data(so, 0x00000000);
+
+		so_method(so, tesla, 0x1538, 1);
+		so_data  (so, 1);
+		so_method(so, tesla, 0x1228, 3);
+		so_data  (so, fb->zsbuf->width);
+		so_data  (so, fb->zsbuf->height);
+		so_data  (so, 0x00010001);
 	}
 
 	so_method(so, tesla, NV50TCL_VIEWPORT_HORIZ, 2);