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authorMarek Olšák <[email protected]>2017-11-07 16:12:56 +0100
committerMarek Olšák <[email protected]>2017-11-07 17:26:36 +0100
commite616743dabe4cdee789c7ad8386fbe9195cbb0ca (patch)
tree4c82df682d5aa7f589538efcd4bec354ba31c2f2
parent24e90047088599e686b636fde9bda3a96f34a35c (diff)
radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven only
Reviewed-by: Nicolai Hähnle <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index b17828e81f3..994ed58a1b8 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1405,11 +1405,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
if (!si_upload_vertex_buffer_descriptors(sctx))
return;
- /* GFX9 scissor bug workaround. This must be done before VPORT scissor
- * registers are changed. There is also a more efficient but more
- * involved alternative workaround.
+ /* Vega10/Raven scissor bug workaround. This must be done before VPORT
+ * scissor registers are changed. There is also a more efficient but
+ * more involved alternative workaround.
*/
- if (sctx->b.chip_class == GFX9 &&
+ if ((sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN) &&
si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
si_emit_cache_flush(sctx);