diff options
author | Dave Airlie <[email protected]> | 2017-09-14 05:03:19 +0100 |
---|---|---|
committer | Dave Airlie <[email protected]> | 2017-09-15 09:49:50 +1000 |
commit | a7a7bf21bdf0cf8e59f8c8e17c2580a363be7055 (patch) | |
tree | 6ed22699d036fb8311dd4109e7f7563a91f19933 | |
parent | 62f2670cbaa8ce22972c21511f0f83e79344b84d (diff) |
st/glsl->tgsi: fix u64 to bool comparisons.
Otherwise we end up using a 32-bit comparison which didn't end well.
Timothy caught this while playing around with some opt passes.
Fixes: 278580729a (st/glsl_to_tgsi: add support for 64-bit integers)
Reviewed-by: Timothy Arceri <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
-rw-r--r-- | src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index cf6e8f8fde1..9b15b618b6e 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -205,6 +205,7 @@ public: st_src_reg st_src_reg_for_double(double val); st_src_reg st_src_reg_for_float(float val); st_src_reg st_src_reg_for_int(int val); + st_src_reg st_src_reg_for_int64(int64_t val); st_src_reg st_src_reg_for_type(enum glsl_base_type type, int val); /** @@ -909,6 +910,19 @@ glsl_to_tgsi_visitor::st_src_reg_for_int(int val) } st_src_reg +glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val) +{ + st_src_reg src(PROGRAM_IMMEDIATE, -1, GLSL_TYPE_INT64); + union gl_constant_value uval[2]; + + memcpy(uval, &val, sizeof(uval)); + src.index = add_constant(src.file, uval, 1, GL_DOUBLE, &src.swizzle); + src.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_X, SWIZZLE_Y); + + return src; +} + +st_src_reg glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type, int val) { if (native_integers) @@ -2141,7 +2155,7 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir, st_src_reg *op) break; } case ir_unop_i642b: - emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], st_src_reg_for_int(0)); + emit_asm(ir, TGSI_OPCODE_U64SNE, result_dst, op[0], st_src_reg_for_int64(0)); break; case ir_unop_i642f: emit_asm(ir, TGSI_OPCODE_I642F, result_dst, op[0]); |