diff options
author | Ian Romanick <[email protected]> | 2016-10-12 15:31:22 -0700 |
---|---|---|
committer | Ian Romanick <[email protected]> | 2017-01-20 15:41:23 -0800 |
commit | 81952814a37ecdbf112454eb7cb0cec090887a8a (patch) | |
tree | a2e9de58b6900bafddfd7200761f6af58fc5ea80 | |
parent | 7122d851aa7d4bae028df2ade1e91ba2347e8bfe (diff) |
glsl: Optimize redundant pack(unpack()) and unpack(pack()) combinations
The lowering passes 64-bit integer operations will generate a lot of
these.
v2: Modify the HANDLE_PACK_UNPACK_INVERSE so that the breaks apply to
the switch instead of the 'do { } while(true)' loop.
Signed-off-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
-rw-r--r-- | src/compiler/glsl/opt_algebraic.cpp | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/compiler/glsl/opt_algebraic.cpp b/src/compiler/glsl/opt_algebraic.cpp index 2829a782514..0ec331524c2 100644 --- a/src/compiler/glsl/opt_algebraic.cpp +++ b/src/compiler/glsl/opt_algebraic.cpp @@ -472,6 +472,34 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir) } break; + /* This macro CANNOT use the do { } while(true) mechanism because + * then the breaks apply to the loop instead of the switch! + */ +#define HANDLE_PACK_UNPACK_INVERSE(inverse_operation) \ + { \ + ir_expression *const op = ir->operands[0]->as_expression(); \ + if (op == NULL) \ + break; \ + if (op->operation == (inverse_operation)) \ + return op->operands[0]; \ + break; \ + } + + case ir_unop_unpack_uint_2x32: + HANDLE_PACK_UNPACK_INVERSE(ir_unop_pack_uint_2x32); + case ir_unop_pack_uint_2x32: + HANDLE_PACK_UNPACK_INVERSE(ir_unop_unpack_uint_2x32); + case ir_unop_unpack_int_2x32: + HANDLE_PACK_UNPACK_INVERSE(ir_unop_pack_int_2x32); + case ir_unop_pack_int_2x32: + HANDLE_PACK_UNPACK_INVERSE(ir_unop_unpack_int_2x32); + case ir_unop_unpack_double_2x32: + HANDLE_PACK_UNPACK_INVERSE(ir_unop_pack_double_2x32); + case ir_unop_pack_double_2x32: + HANDLE_PACK_UNPACK_INVERSE(ir_unop_unpack_double_2x32); + +#undef HANDLE_PACK_UNPACK_INVERSE + case ir_binop_add: if (is_vec_zero(op_const[0])) return ir->operands[1]; |