diff options
author | Chad Versace <[email protected]> | 2017-05-26 18:22:40 -0700 |
---|---|---|
committer | Chad Versace <[email protected]> | 2017-06-01 12:39:35 -0700 |
commit | 77e3c836f893d42a609a22bf32a63174ff948070 (patch) | |
tree | 13a1a206ae18c04f941e5c911d86881711a072a9 | |
parent | 84ede214fc817ac6715894ab199a30477a0b6b23 (diff) |
i965: Fix return type of brw_isl_format_for_mesa_format() [v2]
It returns an isl_format, not uint32_t BRW_FORMAT.
I updated every brw_isl_format_for_mesa_format() found by git-grep.
No change in behavior.
v2: Rebased atop Anuj's patch, which has some of the same fixes.
Reviewed-by: Jason Ekstrand <[email protected]> (v1)
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state.h | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_surface_formats.c | 13 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 |
3 files changed, 10 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index bec7b03c42f..cb341f052e5 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -205,8 +205,7 @@ uint32_t brw_state_batch_size(struct brw_context *brw, uint32_t offset); void gen4_init_vtable_surface_functions(struct brw_context *brw); uint32_t brw_get_surface_tiling_bits(uint32_t tiling); uint32_t brw_get_surface_num_multisamples(unsigned num_samples); - -uint32_t brw_isl_format_for_mesa_format(mesa_format mesa_format); +enum isl_format brw_isl_format_for_mesa_format(mesa_format mesa_format); GLuint translate_tex_target(GLenum target); diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index b176a21c226..f482f22703f 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -28,7 +28,7 @@ #include "brw_state.h" #include "brw_defines.h" -uint32_t +enum isl_format brw_isl_format_for_mesa_format(mesa_format mesa_format) { /* This table is ordered according to the enum ordering in formats.h. We do @@ -300,7 +300,7 @@ brw_init_surface_formats(struct brw_context *brw) gen += 5; for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) { - uint32_t texture, render; + enum isl_format texture, render; bool is_integer = _mesa_is_format_integer_color(format); render = texture = brw_isl_format_for_mesa_format(format); @@ -376,6 +376,8 @@ brw_init_surface_formats(struct brw_context *brw) case ISL_FORMAT_R8G8B8X8_UNORM_SRGB: render = ISL_FORMAT_R8G8B8A8_UNORM_SRGB; break; + default: + break; } /* Note that GL_EXT_texture_integer says that blending doesn't occur for @@ -555,7 +557,8 @@ translate_tex_format(struct brw_context *brw, case MESA_FORMAT_RGBA_ASTC_10x10: case MESA_FORMAT_RGBA_ASTC_12x10: case MESA_FORMAT_RGBA_ASTC_12x12: { - GLuint brw_fmt = brw_isl_format_for_mesa_format(mesa_format); + enum isl_format isl_fmt = + brw_isl_format_for_mesa_format(mesa_format); /** * It is possible to process these formats using the LDR Profile @@ -566,9 +569,9 @@ translate_tex_format(struct brw_context *brw, * processing sRGBs, which are incompatible with this mode. */ if (ctx->Extensions.KHR_texture_compression_astc_hdr) - brw_fmt |= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT; + isl_fmt |= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT; - return brw_fmt; + return isl_fmt; } default: diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 15863cb1637..42c50780eb3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -1587,7 +1587,7 @@ static uint32_t get_image_format(struct brw_context *brw, mesa_format format, GLenum access) { const struct gen_device_info *devinfo = &brw->screen->devinfo; - uint32_t hw_format = brw_isl_format_for_mesa_format(format); + enum isl_format hw_format = brw_isl_format_for_mesa_format(format); if (access == GL_WRITE_ONLY) { return hw_format; } else if (isl_has_matching_typed_storage_image_format(devinfo, hw_format)) { |