diff options
| author | Lucas Stach <[email protected]> | 2016-11-21 12:27:47 +0100 |
|---|---|---|
| committer | Lucas Stach <[email protected]> | 2017-04-11 16:52:22 +0200 |
| commit | 52f6c8cc31f553ba2005892fcf2ca9b5f10bac91 (patch) | |
| tree | 6d47af373c2d8c5c6c434468335def047416c405 | |
| parent | 37622ecc795e655ab0264c44dbe6188d9d9d3813 (diff) | |
etnaviv: align TS surface size to number of pixel pipes
The TS surface gets cleared by a tiled RS fill. If the chip has
more than 1 pixel pipe the size of the TS surface needs to be
aligned so that each pipe address matches a tile start, otherwise
the RS will hang.
Signed-off-by: Lucas Stach <[email protected]>
Reviewed-by: Wladimir J. van der Laan <[email protected]>
| -rw-r--r-- | src/gallium/drivers/etnaviv/etnaviv_resource.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c index 1f0582ce0bf..5f2b63f97c1 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c @@ -52,7 +52,8 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen, /* TS only for level 0 -- XXX is this formula correct? */ pixels = rsc->levels[0].layer_stride / util_format_get_blocksize(rsc->base.format); - ts_layer_stride = align(pixels * screen->specs.bits_per_tile / 0x80, 0x100); + ts_layer_stride = align(pixels * screen->specs.bits_per_tile / 0x80, + 0x100 * screen->specs.pixel_pipes); rt_ts_size = ts_layer_stride * rsc->base.array_size; if (rt_ts_size == 0) return true; |