diff options
author | Francisco Jerez <[email protected]> | 2015-11-23 19:15:26 +0200 |
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committer | Francisco Jerez <[email protected]> | 2015-11-26 14:07:58 +0200 |
commit | 3e6d0d2ca446cb7b3ad8f32bd0d93275a7ed34bc (patch) | |
tree | b56622d159d2a8f86babc08e159f77ed93b07ad1 | |
parent | 6b5268d202acdc69469bd8c1a2f374ccdf414769 (diff) |
i965: Add symbolic defines for some magic dataport surface indices.
Reviewed-by: Kristian Høgsberg <[email protected]>
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index ade3ede082f..a511d5c9a83 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1720,6 +1720,19 @@ enum brw_message_target { #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13 +/* Dataport special binding table indices: */ +#define BRW_BTI_STATELESS 255 +#define GEN7_BTI_SLM 254 +/* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the + * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW, + * CHV and at least some pre-production steppings of SKL due to + * WaForceEnableNonCoherent, HDC memory access may have been overridden by the + * kernel to be non-coherent (matching the behavior of the same BTI on + * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253. + */ +#define GEN8_BTI_STATELESS_IA_COHERENT 255 +#define GEN8_BTI_STATELESS_NON_COHERENT 253 + /* dataport atomic operations. */ #define BRW_AOP_AND 1 #define BRW_AOP_OR 2 |