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authorIndrajit Kumar Das <[email protected]>2020-04-21 16:01:50 +0530
committerIndrajit Kumar Das <[email protected]>2020-04-23 12:02:56 +0530
commit133efa112dfa08f8f28ea2dde42a6072140cd977 (patch)
tree51a23e7898bf4a9f66734c59bb0acb75b32e2d16
parentede36a2efe4d40c0ec81f465fdde761a7c335290 (diff)
radeonsi: enable support for AlphaToCoverageDitherControlNV
Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4543>
-rw-r--r--docs/relnotes/new_features.txt1
-rw-r--r--src/gallium/drivers/radeonsi/si_get.c1
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c18
3 files changed, 15 insertions, 5 deletions
diff --git a/docs/relnotes/new_features.txt b/docs/relnotes/new_features.txt
index cbf7b606860..49541cf4763 100644
--- a/docs/relnotes/new_features.txt
+++ b/docs/relnotes/new_features.txt
@@ -1,6 +1,7 @@
GL_ARB_compute_variable_group_size on i965.
GL_EXT_depth_bounds_test on Iris.
GL_EXT_texture_shadow_lod on radeonsi, nvc0.
+GL_NV_alpha_to_coverage_dither_control on radeonsi
GL_NV_copy_image on all gallium drivers.
GL_NV_pixel_buffer_object on all gallium drivers, i915, i965, swrast.
GL_NV_viewport_array2 on nvc0 (GM200+).
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 4089b944559..0ec0d025b57 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -160,6 +160,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
case PIPE_CAP_GL_SPIRV:
case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
+ case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
return 1;
case PIPE_CAP_QUERY_SO_OVERFLOW:
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 60aa0865502..dbafa173e02 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -461,11 +461,19 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
color_control |= S_028808_ROP3(0xcc);
}
- si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
- S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
- S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
- S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
- S_028B70_OFFSET_ROUND(1));
+ if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
+ si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
+ S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
+ S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
+ S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
+ S_028B70_OFFSET_ROUND(1));
+ } else {
+ si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
+ S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
+ S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
+ S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
+ S_028B70_OFFSET_ROUND(0));
+ }
if (state->alpha_to_coverage)
blend->need_src_alpha_4bit |= 0xf;