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authorSamuel Pitoiset <[email protected]>2016-08-25 18:41:05 +0200
committerSamuel Pitoiset <[email protected]>2016-08-30 18:41:46 +0200
commite0a067ed484698ff62dd8c8750aeb46f18988b17 (patch)
tree12a480fcd719c31603184d1034ccc7a3bab29a26
parent9514c5a30f439f9e3536b6b7f92986c69ae49a20 (diff)
nv50/ir: always emit the NDV bit for OP_QUADOP
This silences a divergent error found with F1 2015. Basically, the NDV bit has to be set when a FSWZ instruction is inside divergent code, but it's not needed otherwise. The correct fix should be to set it only in divergent code situations. GM107 emitter already sets that bit. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp5
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp5
2 files changed, 2 insertions, 8 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index 501d4af7915..570b4a9cc6f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -1320,16 +1320,13 @@ CodeEmitterGK110::emitTXQ(const TexInstruction *i)
void
CodeEmitterGK110::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
{
- code[0] = 0x00000002 | ((qOp & 1) << 31);
+ code[0] = 0x00000202 | ((qOp & 1) << 31); // dall
code[1] = 0x7fc00000 | (qOp >> 1) | (laneMask << 12);
defId(i->def(0), 2);
srcId(i->src(0), 10);
srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 23);
- if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
- code[1] |= 1 << 9; // dall
-
emitPredicate(i);
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 8c9b867e8ba..d83028cd7f7 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -1355,16 +1355,13 @@ CodeEmitterNVC0::emitTXQ(const TexInstruction *i)
void
CodeEmitterNVC0::emitQUADOP(const Instruction *i, uint8_t qOp, uint8_t laneMask)
{
- code[0] = 0x00000000 | (laneMask << 6);
+ code[0] = 0x00000200 | (laneMask << 6); // dall
code[1] = 0x48000000 | qOp;
defId(i->def(0), 14);
srcId(i->src(0), 20);
srcId((i->srcExists(1) && i->predSrc != 1) ? i->src(1) : i->src(0), 26);
- if (i->op == OP_QUADOP && progType != Program::TYPE_FRAGMENT)
- code[0] |= 1 << 9; // dall
-
emitPredicate(i);
}