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authorAnusha Srivatsa <[email protected]>2017-06-22 10:42:32 -0700
committerAnuj Phogat <[email protected]>2017-06-22 14:28:43 -0700
commitde7ed0ba55225c391b439a129c4fc5f57359416f (patch)
tree64e616dfad9e9e7af006417108ae50996948f621
parent43d11b128c220e498416549724df604a68e59394 (diff)
i965/CFL: Add PCI Ids for Coffee Lake.
Coffee Lake has a gen9 graphics following KBL. From 3D perspective, CFL is a clone of KBL/SKL features. v2: Change commit message, correct alignment <Anuj Phogat> v3: Update IDs. v4: Initialize l3_banks, correct nomenclature <Anuj> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Acked-by: Benjamin Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
-rw-r--r--include/pci_ids/i965_pci_ids.h11
-rw-r--r--src/intel/common/gen_device_info.c26
-rw-r--r--src/intel/common/gen_device_info.h1
3 files changed, 38 insertions, 0 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index b296359cde9..57e70b7aed5 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -165,6 +165,17 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 (Kaby Lake GT3)")
CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
+CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
+CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
+CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
diff --git a/src/intel/common/gen_device_info.c b/src/intel/common/gen_device_info.c
index 423748ea08c..f008b76ea47 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -607,6 +607,32 @@ static const struct gen_device_info gen_device_info_glk_2x6 = {
.is_geminilake = true,
};
+static const struct gen_device_info gen_device_info_cfl_gt1 = {
+ GEN9_FEATURES,
+ .is_coffeelake = true,
+ .gt = 1,
+
+ .num_slices = 1,
+ .l3_banks = 2,
+};
+static const struct gen_device_info gen_device_info_cfl_gt2 = {
+ GEN9_FEATURES,
+ .is_coffeelake = true,
+ .gt = 2,
+
+ .num_slices = 1,
+ .l3_banks = 4,
+};
+
+static const struct gen_device_info gen_device_info_cfl_gt3 = {
+ GEN9_FEATURES,
+ .is_coffeelake = true,
+ .gt = 3,
+
+ .num_slices = 2,
+ .l3_banks = 8,
+};
+
#define GEN10_HW_INFO \
.gen = 10, \
.num_thread_per_eu = 7, \
diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h
index cc83857b759..a83251ccfc9 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -46,6 +46,7 @@ struct gen_device_info
bool is_broxton;
bool is_kabylake;
bool is_geminilake;
+ bool is_coffeelake;
bool is_cannonlake;
bool has_hiz_and_separate_stencil;